pto.vmulconv

pto.vmulconv is part of the SFU And DSA Instructions instruction set.

Summary

Fused multiply + ReLU with element-type conversion (hardware fusion).

Mechanism

Fused multiply + ReLU conversion: dst[i] = max(0, lhs[i] * rhs[i]). Multiplies two vectors and applies ReLU with optional element-type conversion in a single fused operation. Combines multiplication, ReLU, and type conversion into one hardware instruction, eliminating intermediate register writes and improving throughput.

Syntax

PTO Assembly Form

vmulconv %dst, %lhs, %rhs, %mask : !pto.vreg<NxT0>

AS Level 1 (SSA)

%result = pto.vmulconv %lhs, %rhs, %mask : (!pto.vreg<NxT0>, !pto.vreg<NxT0>, !pto.mask<G>) -> !pto.vreg<MxT1>

Inputs

Operand Type Description
%lhs !pto.vreg<NxT0> Left-hand source vector
%rhs !pto.vreg<NxT0> Right-hand source vector
%mask !pto.mask<G> Predicate mask; lanes where mask bit is 1 are active

Both source vectors MUST have the same element type T0 and the same vector width N. The mask width MUST match N.

Expected Outputs

Result Type Description
%result !pto.vreg<MxT1> Fused multiply/ReLU/convert result

The destination element type T1 may differ from the source type T0. Only backend-supported source/destination type pairs are legal.

Side Effects

This operation has no architectural side effect beyond producing its destination vector register. It does not implicitly reserve buffers, signal events, or establish memory fences.

Constraints

Constraints

  • Type match: Both source vectors MUST have identical element types.
  • Width match: Both source vectors MUST have the same vector width N.
  • Mask width: %mask MUST have width equal to N.
  • Active lanes: Only lanes where the mask bit is 1 (true) participate in the computation.
  • Type conversion: Only backend-supported source/destination type pairs are legal.
  • Rounding/saturation: Rounding, saturation, and packing rules follow the semantics of this fused operation, not an arbitrary sequence of standalone ops.

Exceptions

Exceptions

  • The verifier rejects illegal operand shapes, unsupported element types, and attribute combinations that are not valid for the selected instruction set or target profile.
  • Any additional illegality stated in the constraints section is also part of the contract.

Target-Profile Restrictions

Target-Profile Restrictions
  • A5 is the most detailed concrete profile in the current manual; CPU simulation and A2/A3-class targets may support narrower subsets or emulate the behavior while preserving the visible PTO contract.
  • Code that depends on an instruction-set-specific type list, distribution mode, or fused form should treat that dependency as target-profile-specific unless the PTO manual states cross-target portability explicitly.

Performance

A5 Latency

SFU operations have higher latency than standard arithmetic ops. Consult the target profile's performance model for cycle-accurate estimates.

A2/A3 Throughput

Metric Value Constant
Startup latency 14 A2A3_STARTUP_BINARY
Completion latency 26 A2A3_COMPL_FP32_EXP
Per-repeat throughput 2 A2A3_RPT_2
Pipeline interval 18 A2A3_INTERVAL

Examples

Fused multiply + ReLU with type conversion

// f16→i8 variant:
for (int i = 0; i < 128; i++)
    dst_i8[i] = f16_to_i8(max(src0_f16[i] * src1_f16[i], 0));

MLIR form

%result = pto.vmulconv %lhs, %rhs, %mask : (!pto.vreg<128xf16>, !pto.vreg<128xf16>, !pto.mask<G>) -> !pto.vreg<128xi8>

Extended Arithmetic

This operation performs element-type conversion as part of the fused sequence. The conversion may involve rounding, saturation, or other type-specific behavior.