B.CATR

assembly

[
  "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}"
]

block

[]

catalog_indices

[
  0
]

catalog_records

[
  {
    "asm": "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}",
    "constraints": [],
    "encoding": [
      {
        "index": 0,
        "mask": "0xfbf07fff",
        "match": "0x00000023",
        "width_bits": 32
      }
    ],
    "encoding_kind": "L32",
    "fields": [
      {
        "name": "DR",
        "pieces": [
          {
            "instruction_lsb": 26,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      },
      {
        "name": "trap",
        "pieces": [
          {
            "instruction_lsb": 19,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      },
      {
        "name": "far",
        "pieces": [
          {
            "instruction_lsb": 18,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      },
      {
        "name": "atom",
        "pieces": [
          {
            "instruction_lsb": 17,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      },
      {
        "name": "aq",
        "pieces": [
          {
            "instruction_lsb": 16,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      },
      {
        "name": "rl",
        "pieces": [
          {
            "instruction_lsb": 15,
            "value_lsb": 0,
            "width": 1
          }
        ],
        "signedness": "encoding-defined",
        "width": 1
      }
    ],
    "form_id": "b_catr_32_e90bd52fa480",
    "length_bits": 32,
    "mnemonic": "B.CATR",
    "semantic_family": "CMD",
    "semantic_group": "Bundle Control Attribute",
    "semantic_handler": "SetBundleControlAttributes",
    "semantic_summary": "Defines one optional block control record for post-commit trap, transactional visibility, acquire/release ordering, remote execution, and dimension-reduction mode.",
    "status": "accepted"
  }
]

classification

[
  "attributes"
]

contract

{
  "block_composition": [
    "Optional header command after BSTART and before the first body instruction. At most one B.CATR may appear in a block."
  ],
  "canonical_assembly": [
    "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}"
  ],
  "defaults": [
    "Omitting B.CATR is equivalent to trap=0, atom=0, aq=0, rl=0, far=0, and DR=0. Every encoded bit is explicit; zero never means an omitted instruction."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}"
  ],
  "exceptions": [
    "A B.CATR outside an active header or a second B.CATR raises Illegal Block Exception before changing pending or architectural state.",
    "DR=1 in CUBE or a non-tile block raises Illegal Block Exception before block effects; VEC, SFU, and TLSU blocks may consume dimension-reduction mode.",
    "A failed or rejected block commit produces no post-commit trap and exposes no partial atomic-block result."
  ],
  "field_contracts": {},
  "field_zero_meanings": {
    "DR": "Encoded zero selects the default multidimensional operation mode.",
    "trap": "Encoded zero disables the synchronous post-commit trap request.",
    "far": "Encoded zero executes the block on the initiating core.",
    "atom": "Encoded zero selects normal operation-specific commit visibility.",
    "aq": "Encoded zero disables acquire ordering.",
    "rl": "Encoded zero disables release ordering."
  },
  "legality": [
    "All six one-bit fields are independently assigned; aq and rl do not require atom=1.",
    "B.CATR is header-only and unique per block.",
    "DR=1 is assigned only for VEC, SFU, and TLSU blocks and rejects for CUBE and non-tile blocks before effects."
  ],
  "memory_effects": [
    "aq prevents later-block memory effects from preceding this block; rl prevents earlier-block memory effects from following it; aq+rl applies both constraints.",
    "atom=1 makes the complete block one non-interleavable all-or-nothing architectural transaction: memory and register-output effects become visible together or remain ineffective.",
    "far=1 may transport inputs and returned results through a remote target selected by routing state, but only the initiating core's final commit is architecturally visible."
  ],
  "operands": [
    {
      "field": "DR",
      "role": "dimension-reduction selector: zero multidimensional; one group-executed reduction mode"
    },
    {
      "field": "trap",
      "role": "synchronous post-commit trap request"
    },
    {
      "field": "far",
      "role": "remote execution request using existing routing state"
    },
    {
      "field": "atom",
      "role": "whole-block transaction selector"
    },
    {
      "field": "aq",
      "role": "acquire ordering bit"
    },
    {
      "field": "rl",
      "role": "release ordering bit"
    }
  ],
  "ordering": [
    "aq prevents later-block memory effects from preceding this block.",
    "rl prevents earlier-block memory effects from following this block.",
    "When both bits are one, both acquire and release constraints apply independently."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "Defines one optional block control record for post-commit trap, transactional visibility, acquire/release ordering, remote execution, and dimension-reduction mode.",
    "trap=1 first commits and clears the block, then saves the selected continuation in a clean trap context; trap return resumes that continuation.",
    "far=1 captures the block inputs for the routing-selected remote target, waits for returned results, and commits those results only on the initiating core.",
    "DR=1 selects operation-defined dimension-reduction behavior for VEC, SFU, or TLSU; it never means dynamic rounding or direct-register addressing."
  ]
}

depends_on

[
  "PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"
]

id

PTO-BLOCK-B-CATR

mnemonic

B.CATR

summary

Defines one optional block control record for post-commit trap, transactional visibility, acquire/release ordering, remote execution, and dimension-reduction mode.

surface

block

{
  "classification": [
    "attributes"
  ],
  "documentation": "docs/block/attributes/B.CATR.md",
  "id": "PTO-BLOCK-B-CATR",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "B.CATR",
    "ndf_clause": "PTO-INST-BLOCK-B-CATR"
  },
  "mnemonic": "B.CATR",
  "readiness_subjects": [
    "ADR-0022",
    "ADR-0032",
    "ADR-0052",
    "ADR-0059",
    "ADR-0075"
  ],
  "semantic_tests": [
    "PTO-AVS-BLOCK-B-CATR-DR-ENGINE-001",
    "PTO-AVS-BLOCK-B-CATR-DUPLICATE-001",
    "PTO-AVS-BLOCK-B-CATR-FIELDS-001",
    "PTO-AVS-BLOCK-B-CATR-PLACEMENT-001",
    "PTO-AVS-BLOCK-B-CATR-POST-TRAP-001"
  ],
  "source": "asl/block/attributes/B.CATR.asl",
  "surface": "block",
  "tests": [
    "PTO-AVS-BLOCK-B-CATR-DECODE-001",
    "PTO-AVS-BLOCK-B-CATR-DR-ENGINE-001",
    "PTO-AVS-BLOCK-B-CATR-DUPLICATE-001",
    "PTO-AVS-BLOCK-B-CATR-FIELDS-001",
    "PTO-AVS-BLOCK-B-CATR-PLACEMENT-001",
    "PTO-AVS-BLOCK-B-CATR-POST-TRAP-001"
  ]
}