{
"block_composition": [
"none"
],
"canonical_assembly": [
"hl.qmt SrcL, ->RegDst",
"hl.qmt.e SrcL, ->RegDst",
"hl.qmt.s SrcL, ->RegDst",
"hl.qmt.r SrcL, ->RegDst",
"hl.qmt.es SrcL, ->RegDst",
"hl.qmt.er SrcL, ->RegDst",
"hl.qmt.i SrcL, SrcR, ->RegDst",
"hl.qmt.ie SrcL, SrcR, ->RegDst",
"hl.qmt.is SrcL, SrcR, ->RegDst",
"hl.qmt.ir SrcL, SrcR, ->RegDst",
"hl.qmt.ies SrcL, SrcR, ->RegDst",
"hl.qmt.ier SrcL, SrcR, ->RegDst"
],
"defaults": [
"The bare form clears i, e, s, and r and queries the remaining number of 64-bit entries.",
"When i=0, the encoded SrcR field is ignored and is not read; canonical assembly omits it.",
"When i=1, SrcR[9:0] supplies capacity 0..1023 and higher source bits are ignored."
],
"encoding_class": "standalone-encoded",
"examples": [
"hl.qmt a0, ->a1",
"hl.qmt.ie t#1, u#1, ->t#2",
"hl.qmt.s sp, ->u#1"
],
"exceptions": [
"s+r and selector failures raise Fault_IllegalInstruction before source reads, queue observation, events, destination writes, or TPC advance.",
"Missing, corrupt, suspend, and restore runtime conditions are reported only in the result status and do not trap."
],
"field_contracts": {},
"field_zero_meanings": {
"SrcL": "Encoded zero names R0; reads produce zero and writes are discarded.",
"SrcR": "Encoded zero names R0; reads produce zero and writes are discarded.",
"RegDst": "Encoded zero names R0; reads produce zero and writes are discarded.",
"i": "Zero selects query rather than initialization.",
"e": "Zero suppresses event notification.",
"s": "Zero suppresses suspension.",
"r": "Zero suppresses restoration."
},
"legality": [
"Reg5 values 0..23 select absolute R0..R23 and 24..31 select the block-relative T#1..T#4 or U#1..U#4 entries; unavailable relative sources and invalid relative destinations reject before queue state changes.",
"Every flag combination is assigned except s+r, including combinations that also set i or e; s+r raises Fault_IllegalInstruction before operand reads or effects.",
"The event suffix is e; b is not an alias."
],
"memory_effects": [
"No direct memory access. Non-relaxed queue operations carry only the GQM ordering edges defined by push and pop."
],
"operands": [
{
"field": "SrcL",
"role": "Reg5 source of the queue address"
},
{
"field": "SrcR",
"role": "Reg5 capacity source, read only when i=1"
},
{
"field": "RegDst",
"role": "Reg5 destination for the operation result"
},
{
"field": "i",
"role": "initialize-or-replace selector"
},
{
"field": "e",
"role": "post-primary-operation event selector"
},
{
"field": "s",
"role": "post-event suspend selector"
},
{
"field": "r",
"role": "post-event restore selector"
}
],
"ordering": [
"For a valid queue, the primary query or initialization occurs first, then e notification, then s suspension or r restoration.",
"Initialization replacement, optional event/state action, and result publication form one instruction effect."
],
"standalone_opcode": true,
"state_effects": [
"i=0 reports remaining 64-bit entries; i=1 atomically creates or replaces the queue and returns allocated bytes.",
"A successful initialization clears prior entries, corruption, and suspension. Zero capacity creates a valid empty writable queue.",
"Result bits [12:0] hold the primary value and [63:62] hold status; unused bits are zero. Status 0 is success, status 1 is missing/corrupt runtime state, and 2..3 are reserved."
]
}