HL.SWI.UPR

assembly

[
  "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}"
]

block

[]

catalog_indices

[
  297
]

catalog_records

[
  {
    "agu": {
      "action": "Store",
      "address_kind": "Immediate",
      "offset_scale": 0,
      "prefetch_returns_address": false,
      "signed_load": false,
      "size_bytes": 4,
      "update_mode": "PreIndex"
    },
    "asm": "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}",
    "constraints": [],
    "encoding": [
      {
        "index": 0,
        "mask": "0x0000707f003f",
        "match": "0x00006059002e",
        "width_bits": 48
      }
    ],
    "encoding_kind": "HL48",
    "fields": [
      {
        "name": "RegDst",
        "pieces": [
          {
            "instruction_lsb": 11,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcD",
        "pieces": [
          {
            "instruction_lsb": 31,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcR",
        "pieces": [
          {
            "instruction_lsb": 36,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "simm17",
        "pieces": [
          {
            "instruction_lsb": 41,
            "value_lsb": 0,
            "width": 7
          },
          {
            "instruction_lsb": 23,
            "value_lsb": 7,
            "width": 5
          },
          {
            "instruction_lsb": 6,
            "value_lsb": 12,
            "width": 5
          }
        ],
        "signedness": "signed",
        "width": 17
      }
    ],
    "form_id": "hl_swi_upr_48_15c2fb96aab0",
    "length_bits": 48,
    "mnemonic": "HL.SWI.UPR",
    "semantic_family": "AGU",
    "semantic_group": "STA/PRE_INDEX",
    "semantic_handler": "ExecuteScalarStore",
    "semantic_summary": "HL.SWI.UPR snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 4-byte value.",
    "status": "accepted"
  }
]

classification

[
  "agu"
]

contract

{
  "block_composition": [
    "none"
  ],
  "canonical_assembly": [
    "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}"
  ],
  "defaults": [
    "Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}"
  ],
  "exceptions": [
    "A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.",
    "A misaligned 4-byte address raises Fault_DataAlignment before translation or permission. A later permission or bounded-memory failure raises Fault_DataPage at the original address.",
    "A fault emits no successful memory event, performs no partial memory or destination effect, preserves pending writeback, and leaves TPC at the faulting instruction.",
    "Recovery performs a full reissue: every address, source snapshot, preflight, memory operation, and destination is recomputed with no retained progress."
  ],
  "field_contracts": {},
  "field_zero_meanings": {
    "RegDst": "Encoded zero discards this result without suppressing the instruction's other effects.",
    "SrcD": "Encoded zero reads the architectural zero GPR.",
    "SrcR": "Encoded zero reads the architectural zero GPR.",
    "simm17": "Encoded zero supplies a zero displacement; it does not denote omission."
  },
  "legality": [
    "Every encoded Reg5 source uses the complete domain: codes 0..23 select absolute GPRs, codes 24..27 select T#1..T#4, and codes 28..31 select U#1..U#4 without consumption.",
    "Every Reg5 destination is assigned: codes 1..23 write GPRs, code 30 pushes U, code 31 pushes T, and codes 0 and 24..29 discard only that result.",
    "simm17 assigns every signed 17-bit value -65536..65535; the encoded byte displacement is that value multiplied by 1.",
    "Each memory address must be aligned to the 4-byte access size; a 4-byte access is the complete transfer unit."
  ],
  "memory_effects": [
    "After complete preflight, perform one little-endian 4-byte store and record one relaxed store event.",
    "A successful overlapping store invalidates the overlapping reservation; a nonoverlapping reservation remains valid."
  ],
  "operands": [
    {
      "field": "RegDst",
      "role": "Reg5 updated-base destination or discard"
    },
    {
      "field": "SrcD",
      "role": "Reg5 first store-data source"
    },
    {
      "field": "SrcR",
      "role": "Reg5 address-base source"
    },
    {
      "field": "simm17",
      "role": "signed address displacement"
    }
  ],
  "ordering": [
    "Snapshot all explicit and implicit scalar sources before destination or memory effects; duplicate and source/destination aliases observe pre-instruction values.",
    "Complete the relaxed 4-byte memory operation, publish any result or writeback, and then advance TPC."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "Sign-extend simm17, multiply it by 1, and add it modulo 2^PTO_XLEN to the SrcR base.",
    "Pre-index mode accesses the updated base and publishes that same updated base only after successful memory completion.",
    "Snapshot every store-data source before any memory effect or destination publication.",
    "Successful execution advances TPC by 6 bytes; a rejected or faulting attempt does not retire."
  ]
}

depends_on

[
  "PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"
]

id

PTO-SCALAR-HL-SWI-UPR

mnemonic

HL.SWI.UPR

summary

HL.SWI.UPR snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 4-byte value.

surface

scalar

{
  "classification": [
    "agu"
  ],
  "documentation": "docs/scalar/agu/HL.SWI.UPR.md",
  "id": "PTO-SCALAR-HL-SWI-UPR",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "HL.SWI.UPR",
    "ndf_clause": "PTO-INST-SCALAR-HL-SWI-UPR"
  },
  "mnemonic": "HL.SWI.UPR",
  "readiness_subjects": [
    "ADR-0029",
    "ADR-0059"
  ],
  "semantic_tests": [
    "PTO-AVS-AGU-HL-SWI-UPR-ALIAS-001",
    "PTO-AVS-AGU-HL-SWI-UPR-BOUND-001",
    "PTO-AVS-AGU-HL-SWI-UPR-EXEC-001",
    "PTO-AVS-AGU-HL-SWI-UPR-FAULT-001"
  ],
  "source": "asl/scalar/agu/HL.SWI.UPR.asl",
  "surface": "scalar",
  "tests": [
    "PTO-AVS-AGU-HL-SWI-UPR-ALIAS-001",
    "PTO-AVS-AGU-HL-SWI-UPR-BOUND-001",
    "PTO-AVS-AGU-HL-SWI-UPR-EXEC-001",
    "PTO-AVS-AGU-HL-SWI-UPR-FAULT-001",
    "PTO-AVS-SCALAR-HL-SWI-UPR-DECODE-001"
  ]
}