操作数与参数
RegDst- Reg5 destination or discard
SrcL- left Reg5 source
SrcR- right Reg5 source
SrcRType- right-source transformation selector
shamt- post-transformation logical-left-shift amount
AND applies the selected right-source transformation before its encoded logical left shift, performs bitwise conjunction, and publishes the PTO_XLEN result.
PTO-SCALAR-ANDand SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}| 字段 | 位宽 | 有符号性 | 架构角色 | 编码零 |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 destination or discard | Encoded zero discards the result. |
SrcL | 5 | encoding-defined | left Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | right Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcRType | 2 | encoding-defined | right-source transformation selector | Encoded zero selects .sw and sign-extends SrcR[31:0]. |
shamt | 5 | encoding-defined | post-transformation logical-left-shift amount | Encoded zero performs no shift. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| shamt | 31:27 | variable |
| SrcRType | 26:25 | variable |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b010 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b0000101 |
{
"reg": [
{
"bits": 7,
"name": "7'b0000101"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b010"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "SrcRType"
},
{
"bits": 5,
"name": "shamt"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}
RegDstSrcLSrcRSrcRTypeshamt下面是该指令所有者中的 Operation;页面没有重写这段行为。
readonly func InstructionContractOperation_AND() => ScalarOperationbegin return ScalarOperation_AND;end;readonly func InstructionContractHandler_AND() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractRightModifier_AND(encoded: bits(2)) => ScalarRightModifierbegin case encoded of when '00' => return ScalarRight_SignedWord; when '01' => return ScalarRight_UnsignedWord; when '10' => return ScalarRight_NegateOrNot; when '11' => return ScalarRight_None; end;end;
pure func InstructionContractPreparedRight_AND( right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let modifier = InstructionContractRightModifier_AND(encoded_modifier); let transformed = ApplyScalarRightModifier(right, modifier, TRUE); let shifted = LSL(transformed, shift_amount); return shifted;end;
pure func InstructionContractResult_AND( left: Word, right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let prepared_right = InstructionContractPreparedRight_AND( right, encoded_modifier, shift_amount); return ScalarBinary(ScalarBinary_AND, left, prepared_right);end;
pure func InstructionContractIsLogicalFamily_AND() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_AND() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}"],"block":[],"catalog_indices":[7],"catalog_records":[{"asm":"and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f","match":"0x00002005","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcRType","pieces":[{"instruction_lsb":25,"value_lsb":0,"width":2}],"signedness":"encoding-defined","width":2},{"name":"shamt","pieces":[{"instruction_lsb":27,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"and_32_b6a903a3ec94","length_bits":32,"mnemonic":"AND","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinary","semantic_summary":"AND applies the selected right-source transformation before its encoded logical left shift, performs bitwise conjunction, and publishes the PTO_XLEN result.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}"],"defaults":["SrcL, SrcR, SrcRType, shamt, and RegDst are required encoded fields; no field can be omitted.","SrcRType=00 selects .sw, SrcRType=01 selects .uw, SrcRType=10 selects .not, and SrcRType=11 selects no modifier. An omitted assembly suffix encodes SrcRType=11.","Encoded shamt zero performs no shift; every value from 0 through 31 is assigned."],"encoding_class":"standalone-encoded","examples":["and a0, a1, ->a2","and t#1, u#1.not<<1, ->u","and zero, a0.sw, ->zero"],"exceptions":["AND raises no arithmetic exception; transformed or shifted-out bits are discarded at PTO_XLEN width.","A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before the destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","SrcRType":"Encoded zero selects .sw and sign-extends SrcR[31:0].","shamt":"Encoded zero performs no shift."},"legality":["SrcL and SrcR codes 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","RegDst codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs.","All four SrcRType encodings are assigned. The logical family uses .not while the arithmetic family uses .neg; AND uses .not.","Every five-bit shamt value from 0 through 31 is legal."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 destination or discard"},{"field":"SrcL","role":"left Reg5 source"},{"field":"SrcR","role":"right Reg5 source"},{"field":"SrcRType","role":"right-source transformation selector"},{"field":"shamt","role":"post-transformation logical-left-shift amount"}],"ordering":["Snapshot both sources before the destination effect so duplicate sources, destination aliases, and queue publication use pre-instruction values.","Publish the result, then advance TPC by four bytes."],"standalone_opcode":true,"state_effects":["Transform SrcR, perform the logical left shift, and compute the PTO_XLEN bitwise conjunction with SrcL.","Apply the selected SrcRType transformation before the logical left shift. The transformation and shift affect SrcR only; SrcL is unchanged before the final operation.","Destination codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs; source queues are non-consuming.","No memory, reservation, descriptor, numeric-flag, trap, block, privilege, or control-flow state changes except the successful TPC advance."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-AND","mnemonic":"AND","summary":"AND applies the selected right-source transformation before its encoded logical left shift, performs bitwise conjunction, and publishes the PTO_XLEN result.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-AND-DECISION-BINDING-001// ndf: kind=contract level=L1 layer=scalar status=accepted// AND MUST implement the mnemonic-local canonical assembly, encoded// legality, defaults, state and memory effects, ordering, and fault boundaries// declared in this owner. The operation region below is the executable binding// for every accepted decision that names this mnemonic.// NDF-END: PTO-AND-DECISION-BINDING-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_AND() => ScalarOperationbegin return ScalarOperation_AND;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_AND() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractRightModifier_AND(encoded: bits(2)) => ScalarRightModifierbegin case encoded of when '00' => return ScalarRight_SignedWord; when '01' => return ScalarRight_UnsignedWord; when '10' => return ScalarRight_NegateOrNot; when '11' => return ScalarRight_None; end;end;
pure func InstructionContractPreparedRight_AND( right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let modifier = InstructionContractRightModifier_AND(encoded_modifier); let transformed = ApplyScalarRightModifier(right, modifier, TRUE); let shifted = LSL(transformed, shift_amount); return shifted;end;
pure func InstructionContractResult_AND( left: Word, right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let prepared_right = InstructionContractPreparedRight_AND( right, encoded_modifier, shift_amount); return ScalarBinary(ScalarBinary_AND, left, prepared_right);end;
pure func InstructionContractIsLogicalFamily_AND() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_AND() => booleanbegin return FALSE;end;// DOC-END: operation
AND 是一条 32 位标量 ALU 指令。它按照完整 XLEN 值结果规则执行按位与;当前指令契约定义结果发布路径以及任何额外状态效果。
执行时先对编码输入做快照,然后按照完整 XLEN 值结果规则执行按位与,最后才产生目标效果。
SrcRType 先转换右源;shamt 再对转换后的值执行逻辑左移,随后才进行算术或逻辑操作。RegDst 是 5 位字段,选择 Reg5 结果目标,或丢弃结果。SrcL 是 5 位字段,通过 Reg5 选择左操作数。SrcR 是 5 位字段,通过 Reg5 选择右操作数。SrcRType 是 2 位字段,选择应用到右源的转换。shamt 是 5 位字段,编码右源转换后执行的逻辑左移量。这些角色来自当前指令契约;T/U 源只被读取和快照,不会因源选择而出队。编码零的精确含义列在下方生成的默认值章节中。
所有标量源都在目标效果前完成快照。完成后的值随后通过 RegDst 按当前标量目标映射发布。
该 ALU 操作不产生内存效果。成功完成架构效果后,TPC 前进 4 字节。
该操作不会产生隐藏的标量发布目标或隐式内存访问。架构变化仅限于当前契约列出的状态效果。
固定宽度算术按当前操作规则回绕,不产生算术异常;固定编码位不匹配或所选 T/U 源不可用时,会在结果发布和 TPC 前进之前触发 Fault_IllegalInstruction。
下方生成的合法性表是已分配字段值、保留编码和目标丢弃编码的权威说明。解码与源可用性检查先于架构效果完成。
本示例只用于演示当前 ASL 所有者,不替代规范操作。
以一个小型 AND 示例说明:SrcL=0xc、SrcR=0xa、SrcRType=11 且 shamt=0 产生 0x8。
正文来自 owning ASL。拖拽或按钮只临时改变当前页面显示顺序。
AND MUST implement the mnemonic-local canonical assembly, encoded legality, defaults, state and memory effects, ordering, and fault boundaries declared in this owner. The operation region below is the executable binding for every accepted decision that names this mnemonic.
PTO-AND-DECISION-BINDING-001asl/scalar/alu/AND.asl346387f0f7bf2ca65a02e1ea3cfe7416427a64d3f2a1ed0f1f6186b6b82b178fa7f15f384656e7b71696fbd01b4a900a32093ffec7f202f6e5504328a83d287311 matching entries
PTO-AVS-SCALAR-AND-ALIASES-001tests/asl/scalar/alu/AND/scalar-bound-and-aliases-001.aslc784fa92252913f6bef2920a8b43bbb77594de9cbd857224befb72717175579dPTO-AVS-SCALAR-AND-DECODE-001tests/asl/scalar/alu/AND/scalar-decode-and-canonical-001.asl4985cb4049b90a6742464ec279bed6e8319e1b57d3b18da7d9d2541996f4c474PTO-AVS-SCALAR-AND-MODIFIER-001tests/asl/scalar/alu/AND/scalar-exec-and-modifier-001.aslebd692ddf57a9fd546cc5e6e458f96cc8fd34677e69e5431ea178d836264d9e2PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/AND.md",
"id": "PTO-SCALAR-AND",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "AND",
"ndf_clause": "PTO-INST-SCALAR-AND"
},
"mnemonic": "AND",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-AND-ALIASES-001",
"PTO-AVS-SCALAR-AND-MODIFIER-001"
],
"source": "asl/scalar/alu/AND.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-AND-ALIASES-001",
"PTO-AVS-SCALAR-AND-DECODE-001",
"PTO-AVS-SCALAR-AND-MODIFIER-001"
]
}0.58.5 · 候选发布7dc8b7e5b121d2b2499a2273bebff29e2cd86812346387f0f7bf2ca65a02e1ea3cfe7416427a64d3f2a1ed0f1f6186b6b82b178f8e391ebf3d72eda55dd30bb952bb6649daf59ac03ecd38ae7a506550bd368226asl/scalar/alu/AND.aslasl/scalar/alu/AND.aslasl/scalar/alu/AND.asl