HL.ANDIW

1// PTO-INSTRUCTION: {"assembly":["hl.andiw SrcL, simm, ->{t, u, Rd}"],"block":[],"catalog_indices":[121],"catalog_records":[{"asm":"hl.andiw SrcL, simm, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f000f","match":"0x00002035000e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"simm24","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":12},{"instruction_lsb":4,"value_lsb":12,"width":12}],"signedness":"signed","width":24}],"form_id":"hl_andiw_48_878c6594c6ff","length_bits":48,"mnemonic":"HL.ANDIW","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinaryW","semantic_summary":"HL.ANDIW applies word bitwise conjunction to SrcL[31:0] and the low word of a sign-extended 24-bit immediate, then sign-extends the 32-bit result.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.andiw SrcL, simm, ->{t, u, Rd}"],"defaults":["SrcL, simm24, and RegDst are required encoded fields; no field can be omitted.","simm24 has the complete signed 24-bit range -8388608 through 8388607; encoded zero is numeric zero."],"encoding_class":"standalone-encoded","examples":["hl.andiw a0, -1, ->a0","hl.andiw t#1, -8388608, ->u","hl.andiw zero, 8388607, ->zero"],"exceptions":["HL.ANDIW raises no arithmetic exception; fixed-width overflow or underflow is discarded.","A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before any destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result and does not modify any GPR or queue.","SrcL":"Encoded zero reads architectural GPR zero.","simm24":"Encoded zero supplies numeric zero."},"legality":["All 32 SrcL encodings are assigned: 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consuming a queue entry.","All 32 RegDst encodings are assigned: codes 0 and 24..29 discard, codes 1..23 write absolute GPRs, code 30 pushes U, and code 31 pushes T.","Every signed 24-bit two's-complement value is assigned. The two 12-bit pieces reconstruct one exact 24-bit value."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 scalar destination or discard selector"},{"field":"SrcL","role":"Reg5 scalar source; only bits 31:0 participate"},{"field":"simm24","role":"signed split 24-bit immediate"}],"ordering":["Snapshot SrcL before the destination effect, including GPR aliases and same-queue read-then-push cases.","Publish the result through RegDst, then advance TPC by six bytes."],"standalone_opcode":true,"state_effects":["Take SrcL[31:0] and the low 32 bits of the sign-extended simm24, compute word bitwise conjunction modulo 2^32, sign-extend the 32-bit result to PTO_XLEN, and publish it through RegDst.","Codes 1..23 write a GPR; codes 0 and 24..29 discard; code 30 pushes U; code 31 pushes T. Relative source reads are non-consuming.","No memory, reservation, descriptor, Tile, block, privilege, numeric-status, branch-target, or other control state changes. Successful execution advances TPC by six bytes."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-ANDIW","mnemonic":"HL.ANDIW","summary":"HL.ANDIW applies word bitwise conjunction to SrcL[31:0] and the low word of a sign-extended 24-bit immediate, then sign-extends the 32-bit result.","surface":"scalar"}2// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}3// NDF-BEGIN: PTO-HL-ANDIW-CONTRACT-0014// ndf: kind=contract level=L1 layer=scalar status=accepted5// HL.ANDIW MUST reconstruct its split simm24 field exactly and apply6// word bitwise conjunction with a sign-extended signed 24-bit immediate.7// Only the low 32 bits of both operands participate; the 32-bit result MUST be sign-extended to PTO_XLEN.8// SrcL MUST use the complete non-consuming Reg5 source map. RegDst MUST9// use the common GPR, discard, U-push, and T-push destination map.10// The source MUST be snapshotted before destination publication.11// Successful execution MUST advance TPC by six bytes and MUST NOT change12// memory, Tile, block, reservation, privilege, numeric-status, or fault state.13// NDF-END: PTO-HL-ANDIW-CONTRACT-00114// DOC-BEGIN: decode15readonly func InstructionContractOperation_HL_ANDIW() => ScalarOperation16begin17    return ScalarOperation_HL_ANDIW;18end;19// DOC-END: decode20// DOC-BEGIN: operation21readonly func InstructionContractHandler_HL_ANDIW() => ScalarSemanticHandler22begin23    return ScalarHandler_ScalarBinaryW;24end;25
26pure func InstructionContractImmediateWidth_HL_ANDIW()27    => integer {1..64}28begin29    return 24;30end;31
32pure func InstructionContractImmediateIsSigned_HL_ANDIW()33    => boolean34begin35    return TRUE;36end;37
38pure func InstructionContractIsWordOperation_HL_ANDIW()39    => boolean40begin41    return TRUE;42end;43
44pure func InstructionContractResult_HL_ANDIW(45    left: Word,46    immediate: bits(24))47    => Word48begin49    let right = SignExtend{PTO_XLEN}(immediate);50    return ScalarBinaryW(51        ScalarBinary_AND,52        left,53        right);54end;55// DOC-END: operation56