HL.MISUB

assembly

[
  "hl.misub SrcL, SrcR, uimm, ->{t, u, Rd}"
]

block

[]

catalog_indices

[
  223
]

catalog_records

[
  {
    "asm": "hl.misub SrcL, SrcR, uimm, ->{t, u, Rd}",
    "constraints": [],
    "encoding": [
      {
        "index": 0,
        "mask": "0x0000707f000f",
        "match": "0x0000104d000e",
        "width_bits": 48
      }
    ],
    "encoding_kind": "HL48",
    "fields": [
      {
        "name": "RegDst",
        "pieces": [
          {
            "instruction_lsb": 23,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcL",
        "pieces": [
          {
            "instruction_lsb": 31,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcR",
        "pieces": [
          {
            "instruction_lsb": 36,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "uimm19",
        "pieces": [
          {
            "instruction_lsb": 41,
            "value_lsb": 0,
            "width": 7
          },
          {
            "instruction_lsb": 4,
            "value_lsb": 7,
            "width": 12
          }
        ],
        "signedness": "unsigned",
        "width": 19
      }
    ],
    "form_id": "hl_misub_48_e9e4c7b23479",
    "length_bits": 48,
    "mnemonic": "HL.MISUB",
    "semantic_family": "ALU",
    "semantic_group": "ALU",
    "semantic_handler": "ScalarMultiplyImmediateAdd",
    "semantic_summary": "HL.MISUB multiplies SrcR by the unsigned 19-bit immediate, subtracts the product from SrcL modulo 2^PTO_XLEN, and publishes the result.",
    "status": "accepted"
  }
]

classification

[
  "alu"
]

contract

{
  "block_composition": [
    "none"
  ],
  "canonical_assembly": [
    "hl.misub SrcL, SrcR, uimm, ->{t, u, Rd}"
  ],
  "defaults": [
    "Every encoded operand and destination field is required; no field can be omitted.",
    "The mnemonic fixes signedness, effective operand width, single-versus-pair result shape, and add-versus-subtract behavior; there is no encoded arithmetic mode.",
    "uimm19 is an unsigned value from 0 through 524287; encoded zero contributes a zero product."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "hl.misub srcl, srcr, uimm, ->{t, u, rd}"
  ],
  "exceptions": [
    "Multiplication and accumulation are fixed-width and raise no arithmetic exception; discarded overflow wraps modulo the defined result width.",
    "An unavailable selected T/U source raises Fault_IllegalInstruction before any destination effect and before TPC advances."
  ],
  "field_contracts": {},
  "field_zero_meanings": {
    "SrcL": "Encoded zero reads the architectural zero GPR.",
    "SrcR": "Encoded zero reads the architectural zero GPR.",
    "RegDst": "Encoded zero discards the result.",
    "uimm19": "Encoded zero selects multiplier zero."
  },
  "legality": [
    "Every source Reg5 code is assigned: 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.",
    "Each destination independently uses the common map: codes 0 and 24..29 discard, codes 1..23 write GPRs, code 30 pushes U, and code 31 pushes T.",
    "Fixed encoding bits must match the canonical form; every encoded source, destination, and immediate value otherwise has assigned behavior."
  ],
  "memory_effects": [
    "none"
  ],
  "operands": [
    {
      "field": "RegDst",
      "role": "Reg5 destination or discard"
    },
    {
      "field": "SrcL",
      "role": "left multiplicand or additive Reg5 source"
    },
    {
      "field": "SrcR",
      "role": "right multiplicand Reg5 source"
    },
    {
      "field": "uimm19",
      "role": "unsigned 19-bit multiplier"
    }
  ],
  "ordering": [
    "Snapshot every source before any destination effect so duplicate selectors and destination aliases observe pre-instruction values.",
    "Publish the result, then advance TPC by six bytes."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "Zero-extend uimm19 to XLEN, multiply it by SrcR, then subtract the product from SrcL modulo 2^PTO_XLEN.",
    "Snapshot every source before the destination effect, publish the XLEN result through the common Reg5 destination map, and do not consume relative sources.",
    "No memory, reservation, descriptor, numeric-status, block, privilege, branch-target, or other control state changes. Successful execution advances TPC by six bytes."
  ]
}

depends_on

[
  "PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"
]

id

PTO-SCALAR-HL-MISUB

mnemonic

HL.MISUB

summary

HL.MISUB multiplies SrcR by the unsigned 19-bit immediate, subtracts the product from SrcL modulo 2^PTO_XLEN, and publishes the result.

surface

scalar

{
  "classification": [
    "alu"
  ],
  "documentation": "docs/scalar/alu/HL.MISUB.md",
  "id": "PTO-SCALAR-HL-MISUB",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "HL.MISUB",
    "ndf_clause": "PTO-INST-SCALAR-HL-MISUB"
  },
  "mnemonic": "HL.MISUB",
  "readiness_subjects": [
    "ADR-0026",
    "ADR-0059"
  ],
  "semantic_tests": [
    "PTO-AVS-SCALAR-HL-MISUB-IMMEDIATE-001"
  ],
  "source": "asl/scalar/alu/HL.MISUB.asl",
  "surface": "scalar",
  "tests": [
    "PTO-AVS-SCALAR-HL-MISUB-DECODE-001",
    "PTO-AVS-SCALAR-HL-MISUB-IMMEDIATE-001"
  ]
}