操作数与参数
RegDst0- remainder Reg5 destination or discard
RegDst1- quotient Reg5 destination or discard
SrcL- dividend Reg5 source
SrcR- divisor Reg5 source
HL.REM computes a signed XLEN remainder/quotient pair from source snapshots, then publishes remainder followed by quotient.
PTO-SCALAR-HL-REMhl.rem SrcL, SrcR, ->Dst0, Dst1| 字段 | 位宽 | 有符号性 | 架构角色 | 编码零 |
|---|---|---|---|---|
RegDst0 | 5 | encoding-defined | remainder Reg5 destination or discard | Encoded zero discards the remainder. |
RegDst1 | 5 | encoding-defined | quotient Reg5 destination or discard | Encoded zero discards the quotient. |
SrcL | 5 | encoding-defined | dividend Reg5 source | Encoded zero reads the architectural zero GPR dividend. |
SrcR | 5 | encoding-defined | divisor Reg5 source | Encoded zero reads the architectural zero GPR divisor and therefore selects defined zero-divisor pair results. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| Constant | 47:41 | 7'b0000000 |
| SrcR | 40:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:28 | 3'b100 |
| RegDst0 | 27:23 | variable |
| Constant | 22:16 | 7'b1010111 |
| RegDst1 | 15:11 | variable |
| Constant | 10:0 | 11'b00000001110 |
{
"reg": [
{
"bits": 11,
"name": "11'b00000001110"
},
{
"bits": 5,
"name": "RegDst1"
},
{
"bits": 7,
"name": "7'b1010111"
},
{
"bits": 5,
"name": "RegDst0"
},
{
"bits": 3,
"name": "3'b100"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 7,
"name": "7'b0000000"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.rem SrcL, SrcR, ->Dst0, Dst1
RegDst0RegDst1SrcLSrcR下面是该指令所有者中的 Operation;页面没有重写这段行为。
readonly func InstructionContractOperation_HL_REM() => ScalarOperationbegin return ScalarOperation_HL_REM;end;readonly func InstructionContractHandler_HL_REM() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarRemainderPair;end;pure func InstructionContractQuotient_HL_REM( dividend: Word, divisor: Word) => Wordbegin return ScalarDivideSigned( dividend, divisor);end;
pure func InstructionContractRemainder_HL_REM( dividend: Word, divisor: Word) => Wordbegin return ScalarRemainderSigned( dividend, divisor);end;
pure func InstructionContractDst0_HL_REM( dividend: Word, divisor: Word) => Wordbegin return InstructionContractRemainder_HL_REM( dividend, divisor);end;
pure func InstructionContractDst1_HL_REM( dividend: Word, divisor: Word) => Wordbegin return InstructionContractQuotient_HL_REM( dividend, divisor);end;// PTO-INSTRUCTION: {"assembly":["hl.rem SrcL, SrcR, ->Dst0, Dst1"],"block":[],"catalog_indices":[232],"catalog_records":[{"asm":"hl.rem SrcL, SrcR, ->Dst0, Dst1","constraints":[],"encoding":[{"index":0,"mask":"0xfe00707f07ff","match":"0x00004057000e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst0","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"RegDst1","pieces":[{"instruction_lsb":11,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"hl_rem_48_3c13e08615aa","length_bits":48,"mnemonic":"HL.REM","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ExecuteScalarRemainderPair","semantic_summary":"HL.REM computes a signed XLEN remainder/quotient pair from source snapshots, then publishes remainder followed by quotient.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.rem SrcL, SrcR, ->Dst0, Dst1"],"defaults":["SrcL, SrcR, RegDst0, and RegDst1 are required encoded fields; no field can be omitted.","There is no encoded arithmetic mode or implicit operand. The mnemonic fixes signedness and operand width; every HL division/remainder spelling returns both quotient and remainder."],"encoding_class":"standalone-encoded","examples":["hl.rem a0, a1, ->a2, a3","hl.rem t#1, zero, ->u, u"],"exceptions":["Division and remainder are total: zero divisors and signed minimum divided by negative one do not raise an arithmetic exception.","An unavailable selected T/U source raises Fault_IllegalInstruction before either destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst0":"Encoded zero discards the remainder.","RegDst1":"Encoded zero discards the quotient.","SrcL":"Encoded zero reads the architectural zero GPR dividend.","SrcR":"Encoded zero reads the architectural zero GPR divisor and therefore selects defined zero-divisor pair results."},"legality":["SrcL and SrcR codes 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","Each destination independently uses the common map: codes 0 and 24..29 discard, codes 1..23 write GPRs, code 30 pushes U, and code 31 pushes T. Duplicate destinations are legal.","Every value of each Reg5 selector is assigned; fixed encoding bits must match the canonical 48-bit form."],"memory_effects":["none"],"operands":[{"field":"RegDst0","role":"remainder Reg5 destination or discard"},{"field":"RegDst1","role":"quotient Reg5 destination or discard"},{"field":"SrcL","role":"dividend Reg5 source"},{"field":"SrcR","role":"divisor Reg5 source"}],"ordering":["Snapshot both sources and compute both results before either destination effect.","Publish remainder to RegDst0, publish quotient to RegDst1, then advance TPC by six bytes."],"standalone_opcode":true,"state_effects":["Interpret the selected operands as signed values, compute both quotient and remainder using the fixed total division rules.","A zero divisor returns quotient zero and the effective dividend as remainder. Signed minimum divided by negative one returns signed minimum quotient and zero remainder.","Publish RegDst0 remainder first, then RegDst1 quotient. If both destinations name one GPR, quotient is final; if both push one queue, quotient is newest and remainder is next-newest.","No memory, reservation, descriptor, numeric-status, block, privilege, branch-target, or other control state changes. Successful execution advances TPC by six bytes."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-REM","mnemonic":"HL.REM","summary":"HL.REM computes a signed XLEN remainder/quotient pair from source snapshots, then publishes remainder followed by quotient.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-HL-REM-RESULT-ORDER-001// ndf: kind=contract level=L1 layer=scalar status=accepted// HL.REM MUST snapshot both sources before destination effects.// RegDst0 MUST receive the remainder before RegDst1 receives the quotient.// Duplicate destinations and queue pushes MUST preserve that write order.// Zero-divisor, signed-overflow, selector, and retirement behavior MUST remain// identical to the corresponding quotient/remainder arithmetic contract.// NDF-END: PTO-HL-REM-RESULT-ORDER-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_REM() => ScalarOperationbegin return ScalarOperation_HL_REM;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_REM() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarRemainderPair;end;pure func InstructionContractQuotient_HL_REM( dividend: Word, divisor: Word) => Wordbegin return ScalarDivideSigned( dividend, divisor);end;
pure func InstructionContractRemainder_HL_REM( dividend: Word, divisor: Word) => Wordbegin return ScalarRemainderSigned( dividend, divisor);end;
pure func InstructionContractDst0_HL_REM( dividend: Word, divisor: Word) => Wordbegin return InstructionContractRemainder_HL_REM( dividend, divisor);end;
pure func InstructionContractDst1_HL_REM( dividend: Word, divisor: Word) => Wordbegin return InstructionContractQuotient_HL_REM( dividend, divisor);end;// DOC-END: operation
HL.REM 是一条 48 位标量 ALU 指令。它根据源快照同时计算有符号余数和商;当前指令契约定义结果发布路径以及任何额外状态效果。
执行时先对编码输入做快照,然后根据源快照同时计算有符号余数和商,最后才产生目标效果。
RegDst0 是 5 位字段,选择余数的 Reg5 目标,或丢弃余数。RegDst1 是 5 位字段,选择商的 Reg5 目标,或丢弃商。SrcL 是 5 位字段,通过 Reg5 选择被除数。SrcR 是 5 位字段,通过 Reg5 选择除数。这些角色来自当前指令契约;T/U 源只被读取和快照,不会因源选择而出队。编码零的精确含义列在下方生成的默认值章节中。
所有结果都在发布前计算完成。随后按编码顺序(RegDst0, RegDst1)更新目标;目标重复指向同一寄存器或队列时也采用这一顺序。
该 ALU 操作不产生内存效果。成功完成架构效果后,TPC 前进 6 字节。
该操作不会产生隐藏的标量发布目标或隐式内存访问。架构变化仅限于当前契约列出的状态效果。
除数为零和有符号最小值除以负一均使用总定义;两个结果都在任何目标写入前计算完成。
下方生成的合法性表是已分配字段值、保留编码和目标丢弃编码的权威说明。解码与源可用性检查先于架构效果完成。
本示例只用于演示当前 ASL 所有者,不替代规范操作。
以一个小型 HL.REM 示例说明:被除数 13 与除数 5 产生余数 3,随后产生商 2。
正文来自 owning ASL。拖拽或按钮只临时改变当前页面显示顺序。
HL.REM MUST snapshot both sources before destination effects. RegDst0 MUST receive the remainder before RegDst1 receives the quotient. Duplicate destinations and queue pushes MUST preserve that write order. Zero-divisor, signed-overflow, selector, and retirement behavior MUST remain identical to the corresponding quotient/remainder arithmetic contract.
PTO-HL-REM-RESULT-ORDER-001asl/scalar/alu/HL.REM.asl694f1d05a09864ba38b2bcef27034e3100b0ccbd43789858b27cd4ac8c8074251351bd491b93403d591dec72fbd64aed9db1d579eca72d86683a9d932ab9efba11 matching entries
PTO-AVS-SCALAR-HL-REM-DECODE-001tests/asl/scalar/alu/HL.REM/scalar-decode-hl-rem-canonical-001.aslc46f81273fa4fe5d0dd30f9d1d61497b01c7ceec7dc67912fd862e8a31659421PTO-AVS-SCALAR-HL-REM-ORDER-002tests/asl/scalar/alu/HL.REM/scalar-exec-hl-rem-order-002.asl1ff36e67c54e7aefceb7ea79b9b8667f8175ae36ddf5b41d149e6e1fee6a2049PTO-AVS-SCALAR-HL-REM-PAIR-001tests/asl/scalar/alu/HL.REM/scalar-exec-hl-rem-pair-001.asl965049302bb1a0a464a0c219bc6c8b123962e082494a2b1fb04875b919543e05PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/HL.REM.md",
"id": "PTO-SCALAR-HL-REM",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.REM",
"ndf_clause": "PTO-INST-SCALAR-HL-REM"
},
"mnemonic": "HL.REM",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-HL-REM-ORDER-002",
"PTO-AVS-SCALAR-HL-REM-PAIR-001"
],
"source": "asl/scalar/alu/HL.REM.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-HL-REM-DECODE-001",
"PTO-AVS-SCALAR-HL-REM-ORDER-002",
"PTO-AVS-SCALAR-HL-REM-PAIR-001"
]
}0.58.5 · 候选发布7dc8b7e5b121d2b2499a2273bebff29e2cd86812694f1d05a09864ba38b2bcef27034e3100b0ccbd43789858b27cd4ac8c8074251cc5b9086a6fc9f772432a6fbd9dba17a43da1b6552ad6f9bef974c579fc207easl/scalar/alu/HL.REM.aslasl/scalar/alu/HL.REM.aslasl/scalar/alu/HL.REM.asl