操作数与参数
RegDst- absolute GPR destination
SrcL- left absolute GPR source
simm24- 24-bit signed immediate or displacement
HL.CMP.ANDI - Combine scalar comparison results with the encoded logical operation.
PTO-SCALAR-HL-CMP-ANDIhl.cmp.andi SrcL, simm, ->{t, u, Rd}| 字段 | 位宽 | 有符号性 | 架构角色 | 编码零 |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | absolute GPR destination | Encoded zero names the architectural zero GPR. |
SrcL | 5 | encoding-defined | left absolute GPR source | Encoded zero names the architectural zero GPR. |
simm24 | 24 | signed | 24-bit signed immediate or displacement | Encoded zero supplies numeric zero for the 24-bit signed immediate or displacement. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| simm24 | 47:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:28 | 3'b010 |
| RegDst | 27:23 | variable |
| Constant | 22:16 | 7'b1010101 |
| simm24 | 15:4 | variable |
| Constant | 3:0 | 4'b1110 |
{
"reg": [
{
"bits": 4,
"name": "4'b1110"
},
{
"bits": 12,
"name": "simm24"
},
{
"bits": 7,
"name": "7'b1010101"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b010"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 12,
"name": "simm24"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.cmp.andi SrcL, simm, ->{t, u, Rd}
RegDstSrcLsimm24下面是该指令所有者中的 Operation;页面没有重写这段行为。
readonly func InstructionContractOperation_HL_CMP_ANDI() => ScalarOperationbegin return ScalarOperation_HL_CMP_ANDI;end;readonly func InstructionContractHandler_HL_CMP_ANDI() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteCompareLogical;end;
pure func InstructionContractCombinesWithOR_HL_CMP_ANDI() => booleanbegin return FALSE;end;
pure func InstructionContractCompareLogicalValue_HL_CMP_ANDI( left: Word, right: Word) => Wordbegin if InstructionContractCombinesWithOR_HL_CMP_ANDI() then return left OR right; end; return left AND right;end;// PTO-INSTRUCTION: {"assembly":["hl.cmp.andi SrcL, simm, ->{t, u, Rd}"],"block":[],"catalog_indices":[129],"catalog_records":[{"asm":"hl.cmp.andi SrcL, simm, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f000f","match":"0x00002055000e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"simm24","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":12},{"instruction_lsb":4,"value_lsb":12,"width":12}],"signedness":"signed","width":24}],"form_id":"hl_cmp_andi_48_de2aae3f4516","length_bits":48,"mnemonic":"HL.CMP.ANDI","semantic_family":"BRU","semantic_group":"BRU","semantic_handler":"ExecuteCompareLogical","semantic_summary":"HL.CMP.ANDI - Combine scalar comparison results with the encoded logical operation.","status":"accepted"}],"classification":["bru"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.cmp.andi SrcL, simm, ->{t, u, Rd}"],"defaults":["The selected assembly form determines which fields are present; every present field carries its encoded value and no encoded zero means omission."],"encoding_class":"standalone-encoded","examples":["hl.cmp.andi SrcL, simm, ->{t, u, Rd}"],"exceptions":["Reserved field encodings raise Fault_IllegalInstruction before effects; handler-specific arithmetic, memory, control-flow, system-register, and privilege faults follow the embedded normative ASL operation."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero names the architectural zero GPR.","SrcL":"Encoded zero names the architectural zero GPR.","simm24":"Encoded zero supplies numeric zero for the 24-bit signed immediate or displacement."},"legality":["Every value in each unconstrained encoded field is assigned; constrained complements are reserved and reject before effects."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"absolute GPR destination"},{"field":"SrcL","role":"left absolute GPR source"},{"field":"simm24","role":"24-bit signed immediate or displacement"}],"ordering":["none"],"standalone_opcode":true,"state_effects":["HL.CMP.ANDI - Combine scalar comparison results with the encoded logical operation.","After decode and legality checks, execute the normative ExecuteCompareLogical ASL handler; no other architectural state is modified."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-CMP-ANDI","mnemonic":"HL.CMP.ANDI","summary":"HL.CMP.ANDI - Combine scalar comparison results with the encoded logical operation.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_CMP_ANDI() => ScalarOperationbegin return ScalarOperation_HL_CMP_ANDI;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_CMP_ANDI() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteCompareLogical;end;
pure func InstructionContractCombinesWithOR_HL_CMP_ANDI() => booleanbegin return FALSE;end;
pure func InstructionContractCompareLogicalValue_HL_CMP_ANDI( left: Word, right: Word) => Wordbegin if InstructionContractCombinesWithOR_HL_CMP_ANDI() then return left OR right; end; return left AND right;end;// DOC-END: operation
HL.CMP.ANDI 对两个解码标量值执行按位与,并发布组合值是否非零。
两个源会在按位与之前完成快照。
组合 word 为零时结果是 XLEN 零,非零时规范化为 XLEN 一。
RegDst 选择编码指定的目的位置或丢弃行为。SrcL 提供左侧标量源。simm24 提供有符号编码立即数。规范化布尔值先通过编码目的位置发布,随后 TPC 前进 6 字节。
该指令不修改提交状态,也不访问内存或保留状态。
编码、保留字段值和源可用性都会在目的、控制或 TPC 效果前检查。
下面的示例只帮助理解当前所有者,不构成第二份语义定义。
hl.cmp.andi SrcL, simm, ->{t, u, Rd} 在条件为真时发布 XLEN 一,否则发布 XLEN 零。
正文来自 owning ASL。拖拽或按钮只临时改变当前页面显示顺序。
No NDF clause is attached to this unit.
10 matching entries
PTO-AVS-BRU-HL-CMP-ANDI-BOUND-001tests/asl/scalar/bru/HL.CMP.ANDI/scalar-bound-hl-cmp-andi-fields-001.asl46cc8a78fb38f78f68859fe1dbdf683f140628468b7475d01bce4602ce41ed6aPTO-AVS-BRU-HL-CMP-ANDI-EXEC-001tests/asl/scalar/bru/HL.CMP.ANDI/scalar-exec-hl-cmp-andi-direct-001.asl2a2b6cd8c6c1fb887ac201f7a35dda7406e40e0362a2cf2e682f4e52be0bc8d6PTO-AVS-SCALAR-HL-CMP-ANDI-DECODE-001tests/asl/scalar/bru/HL.CMP.ANDI/scalar-decode-hl-cmp-andi-canonical-001.asle20f20440b615619fca9f0229e1eef6709d275adc3b27ff33c8aa5345480c63dPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0027…
ADR-0027docs/status/decisions/0027-scalar-bru-totality-and-target-legality.md9289112d250e31f4222dcd27d20bda791be7a1b57764af7ed9b187e767b7acedLoading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"bru"
],
"documentation": "docs/scalar/bru/HL.CMP.ANDI.md",
"id": "PTO-SCALAR-HL-CMP-ANDI",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.CMP.ANDI",
"ndf_clause": "PTO-INST-SCALAR-HL-CMP-ANDI"
},
"mnemonic": "HL.CMP.ANDI",
"readiness_subjects": [
"ADR-0027",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-BRU-HL-CMP-ANDI-BOUND-001",
"PTO-AVS-BRU-HL-CMP-ANDI-EXEC-001"
],
"source": "asl/scalar/bru/HL.CMP.ANDI.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-BRU-HL-CMP-ANDI-BOUND-001",
"PTO-AVS-BRU-HL-CMP-ANDI-EXEC-001",
"PTO-AVS-SCALAR-HL-CMP-ANDI-DECODE-001"
]
}0.58.5 · 候选发布7dc8b7e5b121d2b2499a2273bebff29e2cd86812db59efd07aed73e68c73dbe3a5167e30b42edf8f10fd2b2b6bcc1c885e85b7950eb25a1c7eba0096f4b60c6a1f83edffbff4cd2179e441900f40cb1bf4ecb2ddasl/scalar/bru/HL.CMP.ANDI.aslasl/scalar/bru/HL.CMP.ANDI.asl