MGATHER_CAS

1// PTO-INSTRUCTION: {"assembly":["MGATHER_CAS <bundle operands>"],"block":["BSTART.MGATHER.CAS DataType","B.DATR PadValue, Layout (optional)","B.DIM LB0=ValidCol","B.DIM LB1=ValidRow (optional)","B.DIM LB2=Col (optional)","B.IOT IndexTile, ExpectedTile, mask=PE_MASK","B.IOT ReplacementTile, mask=PE_MASK, <last>, ->DstTile<TSize>","B.IOR BaseGPR, zero, zero, ->zero","BSTOP"],"catalog_indices":[89],"catalog_records":[{"arguments":[{"operand":"destination0"},{"operand":"address"},{"operand":"source0"},{"operand":"source1"},{"operand":"source2"},{"runtime":"CurrentBundlePadValue"}],"command_mnemonic":"BSTART.MGATHER.CAS","contract_status":"reviewed-complete","datr_contract":{"allowed_nonzero_fields":["PadValueOrByteId","Layout"],"pad_union":"pad-value"},"disposition":"accepted-direct-operation","effect_contract":"MGATHER_CAS","family":"TLSU","fault_contract":"ExecuteTileInstruction","function":8,"legality_handler":"TileOperandsLegal_MGATHER_CAS","name":"MGATHER_CAS","operands":[{"field":"destination0","role":"destination"},{"field":"address","role":"base-address"},{"field":"source0","role":"indices"},{"field":"source1","role":"expected"},{"field":"source2","role":"replacement"}],"restart_contract":"CompleteBundleAtWithAcceptedApplicabilityRules","semantic_handler":"MGATHER_CAS","state_effects":["operand:destination0:observed-old-values","operand:address:base-address","operand:source0:byte-displacement-indices","operand:source1:expected-values","operand:source2:replacement-values","runtime:CurrentBundlePadValue:physical-padding"]}],"classification":["memory-and-data-movement","irregular"],"contract":{"block_composition":["BSTART.MGATHER.CAS DataType","B.DATR PadValue, Layout (optional)","B.DIM LB0=ValidCol","B.DIM LB1=ValidRow (optional)","B.DIM LB2=Col (optional)","B.IOT IndexTile, ExpectedTile, mask=PE_MASK","B.IOT ReplacementTile, mask=PE_MASK, <last>, ->DstTile<TSize>","B.IOR BaseGPR, zero, zero, ->zero","BSTOP"],"canonical_assembly":["MGATHER_CAS <bundle operands>"],"defaults":["B.IOR is required. RegSrc0 names the PE-private absolute GPR containing the byte-address base; zero selects architectural base address zero. Unused B.IOR fields must encode zero.","LB0 is required and supplies ValidCol. Omitted LB1 defaults ValidRow to one. Omitted LB2 defaults physical Col to ValidCol. Explicit zero is illegal for every present dimension.","Omitted B.DATR selects PadValue=Null and Layout=NORM. The pad value defines every physical destination element outside ValidRow x ValidCol.","Each IndexTile logical element is a signed or unsigned byte displacement. Comparison and replacement values use the selected transfer DataType."],"encoding_class":"selector-encoded-block-operation","examples":["BSTART.MGATHER.CAS DataType; B.DATR PadValue, Layout (optional); B.DIM LB0=ValidCol; B.DIM LB1=ValidRow (optional); B.DIM LB2=Col (optional); B.IOT IndexTile, ExpectedTile, mask=PE_MASK; B.IOT ReplacementTile, mask=PE_MASK, <last>, ->DstTile<TSize>; B.IOR BaseGPR, zero, zero, ->zero; BSTOP"],"exceptions":["A missing B.IOR, missing LB0, malformed two-command B.IOT sequence, non-integer IndexTile, shape or type mismatch, packed four-bit transfer DataType, or invalid dimensions raises Fault_TileLegality before destination allocation, atomic events, or memory writes.","Every valid-region read and write address is probed before the first compare-and-swap. Any access fault leaves the destination unallocated and produces no partial atomic event, memory write, or payload effect.","CompleteBundleAtWithAcceptedApplicabilityRules supplies restart and completion behavior after an accepted operation."],"field_contracts":{},"field_zero_meanings":{},"legality":["MGATHER_CAS is selected only by BSTART.MGATHER.CAS function 8 in the TLSU selector space; it has no standalone opcode.","Exactly two Local B.IOT bindings are required. The first supplies IndexTile and ExpectedTile without a destination and has L=0. The second supplies ReplacementTile and a newly allocated destination and has L=1. Both carry one common PE_MASK; B.IOS is not accepted.","IndexTile must be allocated, fully defined, generically indexable, and use S32, U32, S64, or U64. Each logical element is sign- or zero-extended as a byte displacement.","ExpectedTile and ReplacementTile must be allocated, fully defined, use the selected transfer DataType, and match the resolved ValidRow x ValidCol. Comparison uses their encoded element values.","Packed four-bit transfer DataTypes E2M1X2, E1M2X2, HiF4X2, S4X2, and U4X2 are rejected because the block carries no nibble selector.","Destination physical Rows are derived from TSize, physical Col, and transfer DataType. Rows and Col are powers of two and the physical region contains ValidRow x ValidCol.","B.IOT PE_MASK=0000 is a strict no-op before schema, GPR, source, dimension, allocation, address, or fault checks.","B.DATR applicability allows only PadValueOrByteId as PadValue and Layout."],"memory_effects":["For each valid coordinate, atomically read the selected transfer-typed element at BaseGPR plus the corresponding signed or unsigned byte displacement, compare it with ExpectedTile, conditionally store ReplacementTile, and place the observed old value in the destination.","All lane addresses are preflighted before the first atomic event. Duplicate addresses are legal and their per-lane atomic operations serialize in an implementation-defined order; no row-major or other fixed order is architectural.","After every selected lane completes, publish the observed valid region and pad every remaining physical destination coordinate atomically."],"operands":[{"field":"destination0","role":"observed-old-values destination"},{"field":"address","role":"base-address"},{"field":"source0","role":"byte-displacement indices"},{"field":"source1","role":"expected values"},{"field":"source2","role":"replacement values"}],"ordering":["Each lane is one atomic read-modify-write governed by the block memory-order attributes.","Duplicate-address lanes serialize in an implementation-defined order. No additional inter-PE order is guaranteed."],"standalone_opcode":false,"state_effects":["Allocate a new Local destination descriptor using B.IOT TSize, resolved dimensions, selected transfer DataType, selected Layout, and PE_MASK.","Initialize every physical destination coordinate from the selected PadValue carrier before enabled valid-lane writes.","On success overwrite enabled valid coordinates with loaded or observed values, mark the full physical destination defined, set contents_defined=TRUE, and publish atomically."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"engine":"TLSU","id":"PTO-TILE-MGATHER-CAS","mnemonic":"MGATHER_CAS","summary":"Atomically compare and conditionally replace GM elements at signed or unsigned byte displacements.","surface":"tile"}2// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}3// NDF-BEGIN: PTO-MGATHER-CAS-ATOMIC-0014// ndf: kind=contract level=L1 layer=tile status=accepted5// MGATHER_CAS MUST accept non-packed B8-NP, B16, B32, or B64 transfer data with6// S32, U32, S64, or U64 byte-displacement indices and preserve raw carrier7// bits without numeric-validity rejection. Each valid lane MUST perform one8// atomic compare-and-swap at the9// signed or unsigned byte displacement supplied by IndexTile and MUST place10// the value observed by that atomic operation in the corresponding destination11// element. Duplicate-address lanes MUST serialize in an implementation-defined12// order and MUST NOT expose a fixed row-major ordering requirement.13// NDF-END: PTO-MGATHER-CAS-ATOMIC-00114// NDF-BEGIN: PTO-MGATHER-CAS-PUBLICATION-00115// ndf: kind=contract level=L1 layer=tile status=accepted16// MGATHER_CAS MUST preflight every valid-region read and write address before17// its first atomic effect. On success it MUST publish one fully defined18// destination whose non-valid physical elements contain the selected pad value.19// NDF-END: PTO-MGATHER-CAS-PUBLICATION-00120// DOC-BEGIN: decode21readonly func InstructionContractOperation_MGATHER_CAS() => TileOperation22begin23    return TileOperation_MGATHER_CAS;24end;25// DOC-END: decode26// DOC-BEGIN: operation27readonly func InstructionContractHandler_MGATHER_CAS() => TileSemanticHandler28begin29    return TileHandler_MGATHER_CAS;30end;31
32pure func InstructionContractUsesByteDisplacements_MGATHER_CAS()33    => boolean34begin35    return TRUE;36end;37
38pure func InstructionContractUsesMaskTile_MGATHER_CAS()39    => boolean40begin41    return FALSE;42end;43
44pure func InstructionContractIsAtomicMemoryOperation_MGATHER_CAS()45    => boolean46begin47    return TRUE;48end;49
50pure func InstructionContractWritesMemory_MGATHER_CAS()51    => boolean52begin53    return TRUE;54end;55// DOC-END: operation56