BSTART.TPREFETCH

assembly

[
  "BSTART.TPREFETCH DataType"
]

block

[]

catalog_indices

[
  49
]

catalog_records

[
  {
    "asm": "BSTART.TPREFETCH DataType",
    "constraints": [
      {
        "field": "DataType",
        "operator": "one-of",
        "values": [
          0,
          1,
          2,
          3,
          4,
          5,
          6,
          7,
          8,
          9,
          10,
          11,
          12,
          13,
          14,
          16,
          17,
          18,
          19,
          20,
          24,
          25,
          26,
          27,
          28
        ]
      }
    ],
    "encoding": [
      {
        "index": 0,
        "mask": "0x07ffffff",
        "match": "0x00311181",
        "width_bits": 32
      }
    ],
    "encoding_kind": "L32",
    "fields": [
      {
        "name": "DataType",
        "pieces": [
          {
            "instruction_lsb": 27,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      }
    ],
    "form_id": "bstart_tprefetch_32_d5f83e5aadf6",
    "length_bits": 32,
    "mnemonic": "BSTART.TPREFETCH",
    "semantic_family": "CMD",
    "semantic_group": "Bundle Split",
    "semantic_handler": "ExecuteBundleStart",
    "semantic_summary": "Starts a destination-free, four-PE TLSU prefetch block with an explicit element data type.",
    "status": "accepted"
  }
]

classification

[
  "execution"
]

contract

{
  "block_composition": [
    "BSTART.TPREFETCH DataType; optional B.DATR Layout; optional B.DIM LB0/ValidCol, LB1/ValidRow, LB2/Col; optional B.IOR base,row_stride; BSTOP",
    "B.IOT and B.IOS are not members of a TPREFETCH block."
  ],
  "canonical_assembly": [
    "BSTART.TPREFETCH DataType"
  ],
  "defaults": [
    "DataType is explicit and B.DATR omission selects NORM layout.",
    "Omitted LB0 and LB1 each default to one; omitted LB2 defaults to resolved ValidCol.",
    "Omitted B.IOR supplies base zero and row stride equal to resolved Col independently for every PE. Explicit zero selectors read the architectural zero GPR and therefore supply actual zero values."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "BSTART.TPREFETCH FP16; B.DIM zero, 64, ->LB0; B.DIM zero, 4, ->LB1; B.DIM zero, 64, ->LB2; B.IOR zero, a0; BSTOP"
  ],
  "exceptions": [
    "Reserved DataType, unsupported Layout, explicit zero or out-of-range dimensions, non-power-of-two Col, malformed B.IOR, any B.IOT/B.IOS, or any participating-PE memory fault rejects before the first request or memory event.",
    "A memory fault is precise for the complete four-PE block and recovery reissues the complete combined footprint."
  ],
  "field_contracts": {
    "DataType": {
      "ref": "PTO-FIELD-BLOCK-DATATYPE"
    }
  },
  "field_zero_meanings": {
    "DataType": "Encoded zero selects FP64."
  },
  "legality": [
    "bstart_tprefetch_32_d5f83e5aadf6.DataType accepts only 0..14, 16..20, 24..28; all other encodings are reserved.",
    "TPREFETCH has implicit PE participation 1111 and no Local or Shared Tile binding.",
    "ValidCol and ValidRow are positive, Col is a nonzero power of two, and ValidCol does not exceed Col."
  ],
  "memory_effects": [
    "For every PE and every element in ValidRow x ValidCol, access GM at base + ((row * row_stride_elements + column) * element_size), with packed four-bit types using the same logical-element byte addressing as TLOAD.",
    "The operation produces the same typed-element load-event decomposition as TLOAD but allocates and writes no destination Tile. Cache level, placement, and retention are not architectural results."
  ],
  "operands": [
    {
      "field": "DataType",
      "role": "prefetched element data type"
    },
    {
      "field": "B.IOR.RegSrc0",
      "role": "each PE's private-GPR GM base"
    },
    {
      "field": "B.IOR.RegSrc1",
      "role": "each PE's private-GPR logical row stride in elements"
    },
    {
      "field": "B.DIM.LB0",
      "role": "ValidCol"
    },
    {
      "field": "B.DIM.LB1",
      "role": "ValidRow"
    },
    {
      "field": "B.DIM.LB2",
      "role": "physical Col"
    }
  ],
  "ordering": [
    "The four PE footprints are one combined preflighted block attempt; no request or event becomes effective until every address, translation, permission, and access check succeeds.",
    "All successful accesses participate in PTO-TSO using the block aq/rl attributes exactly as TLOAD."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "Starts a destination-free TLSU block whose successful architectural effects are limited to its defined typed memory accesses and ordering events.",
    "No Tile or Shared descriptor, allocation, payload, definedness, publication, or lifetime state changes."
  ]
}

depends_on

[
  "PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"
]

id

PTO-BLOCK-BSTART-TPREFETCH

mnemonic

BSTART.TPREFETCH

summary

Prefetches one typed, strided GM rectangle for each of the four PEs without a Tile destination.

surface

block

{
  "classification": [
    "execution"
  ],
  "documentation": "docs/block/execution/BSTART.TPREFETCH.md",
  "id": "PTO-BLOCK-BSTART-TPREFETCH",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "BSTART.TPREFETCH",
    "ndf_clause": "PTO-INST-BLOCK-BSTART-TPREFETCH"
  },
  "mnemonic": "BSTART.TPREFETCH",
  "readiness_subjects": [
    "ADR-0020",
    "ADR-0032",
    "ADR-0033",
    "ADR-0052",
    "ADR-0055",
    "ADR-0056",
    "ADR-0059",
    "ADR-0078"
  ],
  "semantic_tests": [
    "PTO-AVS-BLOCK-TPREFETCH-DEFAULTS-001",
    "PTO-AVS-BLOCK-TPREFETCH-FAULT-001",
    "PTO-AVS-BLOCK-TPREFETCH-FOOTPRINT-001",
    "PTO-AVS-BLOCK-TPREFETCH-PACKED-001",
    "PTO-AVS-BLOCK-TPREFETCH-SCHEMA-001"
  ],
  "source": "asl/block/execution/BSTART.TPREFETCH.asl",
  "surface": "block",
  "tests": [
    "PTO-AVS-BLOCK-BSTART-TPREFETCH-DECODE-001",
    "PTO-AVS-BLOCK-TPREFETCH-DEFAULTS-001",
    "PTO-AVS-BLOCK-TPREFETCH-FAULT-001",
    "PTO-AVS-BLOCK-TPREFETCH-FOOTPRINT-001",
    "PTO-AVS-BLOCK-TPREFETCH-PACKED-001",
    "PTO-AVS-BLOCK-TPREFETCH-SCHEMA-001"
  ]
}