Operands and parameters
DstBegin- first register in the inclusive R2..R23 ring range
DstEnd- last register in the inclusive R2..R23 ring range
uimm- frame byte count, encoded in multiples of eight
Restores a restartable stack frame and returns through the pre-restore architectural return address.
PTO-BLOCK-FRET-RAFRET.RA [RegDst0 ~ RegDstn], sp!, uimm| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
DstBegin | 5 | encoding-defined | first register in the inclusive R2..R23 ring range | Encoded zero is outside the callee-save ring and is reserved. |
DstEnd | 5 | encoding-defined | last register in the inclusive R2..R23 ring range | Encoded zero is outside the callee-save ring and is reserved. |
uimm | 15 | unsigned | frame byte count, encoded in multiples of eight | Encoded zero is a real zero-byte frame size and is illegal for every nonempty range. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| uimm | 31:25 | variable |
| DstEnd | 24:20 | variable |
| DstBegin | 19:15 | variable |
| Constant | 14:12 | 3'b010 |
| uimm | 11:7 | variable |
| Constant | 6:0 | 7'b1000001 |
{
"reg": [
{
"bits": 7,
"name": "7'b1000001"
},
{
"bits": 5,
"name": "uimm"
},
{
"bits": 3,
"name": "3'b010"
},
{
"bits": 5,
"name": "DstBegin"
},
{
"bits": 5,
"name": "DstEnd"
},
{
"bits": 7,
"name": "uimm"
}
],
"config": {
"bits": 32,
"fontsize": 13,
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}FRET.RA [RegDst0 ~ RegDstn], sp!, uimm
DstBeginDstEnduimmDecode and Operation come directly from the instruction owner and remain separated by execution phase.
readonly func InstructionContractMatches_FRET_RA(operation: CommandOperation) => booleanbegin return (operation == CommandOperation_fret_ra_32_659c886221c1);end;readonly func InstructionContractHandler_FRET_RA() => CommandSemanticHandlerbegin return CommandHandler_ExecuteFrameReturnAddress;end;
func ExecuteFRETRA(begin_reg: Reg5Selector, end_reg: Reg5Selector, frame_size: Word)begin ReturnFromFrame(begin_reg, end_reg, frame_size, TRUE);end;
pure func InstructionContractUsesInclusiveRegisterRange_FRET_RA() => booleanbegin return TRUE;end;
pure func InstructionContractRejectsInvalidFrameRange_FRET_RA() => booleanbegin return TRUE;end;// PTO-INSTRUCTION: {"assembly":["FRET.RA [RegDst0 ~ RegDstn], sp!, uimm"],"block":[],"catalog_indices":[64],"catalog_records":[{"asm":"FRET.RA [RegDst0 ~ RegDstn], sp!, uimm","constraints":[{"field":"DstBegin","operator":"one-of","values":[2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]},{"field":"DstEnd","operator":"one-of","values":[2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]}],"encoding":[{"index":0,"mask":"0x0000707f","match":"0x00002041","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"DstBegin","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"DstEnd","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"uimm","pieces":[{"instruction_lsb":25,"value_lsb":3,"width":7},{"instruction_lsb":7,"value_lsb":10,"width":5}],"signedness":"unsigned","width":15}],"form_id":"fret_ra_32_659c886221c1","length_bits":32,"mnemonic":"FRET.RA","semantic_family":"CMD","semantic_group":"Bundle Split","semantic_handler":"ExecuteFrameReturnAddress","semantic_summary":"Restores a restartable stack frame and returns through the pre-restore architectural return address.","status":"accepted"}],"classification":["lifecycle"],"contract":{"block_composition":["none"],"canonical_assembly":["FRET.RA [RegDst0 ~ RegDstn], sp!, uimm"],"defaults":["The inclusive register range is the ring R2..R23. Singleton, full-ring, and wraparound ranges are assigned.","uimm is always present and represents a byte count in multiples of eight; encoded zero is real zero and is illegal because every assigned range contains at least one register.","The return target is the architectural ra value snapshotted before any restored register can overwrite ra."],"encoding_class":"standalone-encoded","examples":["FRET.RA [RegDst0 ~ RegDstn], sp!, uimm"],"exceptions":["Reserved endpoints or an insufficient frame size raise Fault_IllegalInstruction before sp, register, memory, target, progress, or TPC effects.","Each eight-byte stack access is a restart boundary. A recoverable access fault preserves earlier committed events and retries exactly the first uncommitted event from trap-preserved template state.","An odd pre-restore ra raises Fault_InstructionPC before sp, memory, destination, frame, or return effects."],"field_contracts":{},"field_zero_meanings":{"DstBegin":"Encoded zero is outside the callee-save ring and is reserved.","DstEnd":"Encoded zero is outside the callee-save ring and is reserved.","uimm":"Encoded zero is a real zero-byte frame size and is illegal for every nonempty range."},"legality":["DstBegin and DstEnd select the inclusive R2..R23 callee-save ring; every endpoint outside 2..23 is reserved before effects.","If the range contains N registers, uimm must be at least 8*N bytes. The encoding supplies only multiples of eight."],"memory_effects":["Load one aligned eight-byte value per selected destination using the same restartable frame-slot order as FEXIT."],"operands":[{"field":"DstBegin","role":"first register in the inclusive R2..R23 ring range"},{"field":"DstEnd","role":"last register in the inclusive R2..R23 ring range"},{"field":"uimm","role":"frame byte count, encoded in multiples of eight"}],"ordering":["Snapshot and validate the pre-restore return target, add uimm to sp, then restore descending slots in register-ring order.","After the final restore, publish the snapshotted target to TPC; the command does not perform a sequential TPC increment."],"standalone_opcode":true,"state_effects":["Restoring a range that contains ra updates the architectural ra value without changing the already snapshotted return target.","Completion decrements nonzero frame depth, publishes the last-frame tuple, clears progress, and transfers to the validated target."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-BLOCK-FRET-RA","mnemonic":"FRET.RA","summary":"Restores a restartable stack frame and returns through the pre-restore architectural return address.","surface":"block"}// NDF-BEGIN: PTO-FRET-RA-RESTARTABLE-FRAME-001// ndf: kind=contract level=L1 layer=block status=accepted// FRET.RA MUST snapshot and validate the pre-restore ra target before frame// effects, restore the inclusive ring, then publish only that retained target.// NDF-END: PTO-FRET-RA-RESTARTABLE-FRAME-001// DOC-BEGIN: decodereadonly func InstructionContractMatches_FRET_RA(operation: CommandOperation) => booleanbegin return (operation == CommandOperation_fret_ra_32_659c886221c1);end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_FRET_RA() => CommandSemanticHandlerbegin return CommandHandler_ExecuteFrameReturnAddress;end;
func ExecuteFRETRA(begin_reg: Reg5Selector, end_reg: Reg5Selector, frame_size: Word)begin ReturnFromFrame(begin_reg, end_reg, frame_size, TRUE);end;
pure func InstructionContractUsesInclusiveRegisterRange_FRET_RA() => booleanbegin return TRUE;end;
pure func InstructionContractRejectsInvalidFrameRange_FRET_RA() => booleanbegin return TRUE;end;// DOC-END: operation// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}
FRET.RA is a standalone frame-lifecycle command that validates its register range and stack state before publishing frame or control-flow effects.
FRET.RA executes as a standalone 32-bit command and does not require placement inside a BSTART/BSTOP body.
The accepted carrier uses the L32 encoding class and resolves every displayed field before the command reads bindings or changes state.
The command snapshots every required source before its first visible effect, then follows the owner-defined commit or restart boundary.
DstBegin — first register in the inclusive R2..R23 ring range; DstEnd — last register in the inclusive R2..R23 ring range; uimm — frame byte count, encoded in multiples of eight.Source validation and snapshot precede every register, queue, frame, memory, event, or control-flow effect.
The command commits at the restart boundaries named by its memory contract; earlier committed steps remain visible only where the owner explicitly permits restart progress.
Fixed bits, reserved values, selector domains, and required Block placement are checked before architectural effects.
The current owner reports invalid schema, state, address, or continuation conditions through Fault_IllegalInstruction, Fault_InstructionPC; no prose on this page creates an additional fault rule.
Rejection occurs before effects unless the current owner explicitly defines a restart boundary with retained progress; completion order remains the ASL order.
This example demonstrates placement and carrier flow only; exact behavior remains in the current ASL and instruction contract.
FRET.RA [RegDst0 ~ RegDstn], sp!, uimmThe shown accepted spelling resolves its fields from the current carrier, snapshots required sources, and then follows the owner-defined state and ordering transition.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
FRET.RA MUST snapshot and validate the pre-restore ra target before frame effects, restore the inclusive ring, then publish only that retained target.
PTO-FRET-RA-RESTARTABLE-FRAME-001asl/block/lifecycle/FRET.RA.asl187abc3675a61de6a2491f51da6d18f60029ee7d5637226b241c91429cd7f09c788c254cce072842b6ba831e70497eb434a7c8171d1a5e502a32c53bfa8dfdde12 matching entries
PTO-AVS-BLOCK-FRET-RA-ACCESS-RECOVERY-002tests/asl/block/lifecycle/FRET.RA/block-fault-fret-ra-access-recovery-002.aslb70f1704ba321855902cfc6b0281eab4c15c86b9b5ed5ff7d3769d63d22bf2a0PTO-AVS-BLOCK-FRET-RA-DECODE-001tests/asl/block/lifecycle/FRET.RA/block-decode-fret-ra-canonical-001.asl9436eba56c9221a552def664f351ae748f17e4c730b68487d584ab182ada8160PTO-AVS-BLOCK-FRET-RA-TARGET-001tests/asl/block/lifecycle/FRET.RA/block-exec-fret-ra-target-001.asle622381560c4ac301c5ed7756e3138632a216239d8f5c3f95ec9c34de251603bPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0032…
ADR-0032docs/status/decisions/0032-bundle-command-totality-and-profile-boundaries.mde1f91826817343c0977a565a91e495a15397b83fa2af227124f225821ffa54aeLoading ADR-0052…
ADR-0052docs/status/decisions/0052-direct-tile-and-bundle-catalog-closure.md5fdb38bf480e37affe5075f93b35a57d32803018c986bfe05160f188a19ccaf6Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"lifecycle"
],
"documentation": "docs/block/lifecycle/FRET.RA.md",
"id": "PTO-BLOCK-FRET-RA",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "FRET.RA",
"ndf_clause": "PTO-INST-BLOCK-FRET-RA"
},
"mnemonic": "FRET.RA",
"readiness_subjects": [
"ADR-0032",
"ADR-0052",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-BLOCK-FRET-RA-ACCESS-RECOVERY-002",
"PTO-AVS-BLOCK-FRET-RA-TARGET-001"
],
"source": "asl/block/lifecycle/FRET.RA.asl",
"surface": "block",
"tests": [
"PTO-AVS-BLOCK-FRET-RA-ACCESS-RECOVERY-002",
"PTO-AVS-BLOCK-FRET-RA-DECODE-001",
"PTO-AVS-BLOCK-FRET-RA-TARGET-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd86812187abc3675a61de6a2491f51da6d18f60029ee7d5637226b241c91429cd7f09c8ea690518b5b397beb4437f812080ed9344eb0aa9735198aeb9243d71e42affdasl/block/lifecycle/FRET.RA.aslasl/block/lifecycle/FRET.RA.aslasl/block/lifecycle/FRET.RA.asl