HL.LB.PO snapshots its scalar sources, forms its encoded address, and loads one aligned little-endian 1-byte value.
PTO-SCALAR-HL-LB-POhl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst0 | 5 | encoding-defined | Reg5 first loaded-value destination or discard | Encoded zero discards this result without suppressing the instruction's other effects. |
RegDst1 | 5 | encoding-defined | Reg5 updated-base destination or discard | Encoded zero discards this result without suppressing the instruction's other effects. |
SrcL | 5 | encoding-defined | Reg5 address-base source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | Reg5 register-offset source | Encoded zero reads the architectural zero GPR. |
SrcRType | 2 | encoding-defined | register-offset transformation selector | Encoded zero leaves the complete PTO_XLEN register-offset value unchanged. |
shamt | 5 | encoding-defined | post-transformation logical-left-shift amount | Encoded zero performs no shift. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| shamt | 47:43 | variable |
| SrcRType | 42:41 | variable |
| SrcR | 40:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:28 | 3'b000 |
| RegDst0 | 27:23 | variable |
| Constant | 22:16 | 7'b0001001 |
| RegDst1 | 15:11 | variable |
| Constant | 10:0 | 11'b00000111110 |
{
"reg": [
{
"bits": 11,
"name": "11'b00000111110"
},
{
"bits": 5,
"name": "RegDst1"
},
{
"bits": 7,
"name": "7'b0001001"
},
{
"bits": 5,
"name": "RegDst0"
},
{
"bits": 3,
"name": "3'b000"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "SrcRType"
},
{
"bits": 5,
"name": "shamt"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1
RegDst0RegDst1SrcLSrcRSrcRTypeshamtThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_HL_LB_PO() => ScalarOperationbegin return ScalarOperation_HL_LB_PO;end;readonly func InstructionContractHandler_HL_LB_PO() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarLoad;end;
pure func InstructionContractAGUAction_HL_LB_PO() => ScalarAGUActionbegin return ScalarAGU_Load;end;
pure func InstructionContractAGUAddressKind_HL_LB_PO() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_HL_LB_PO() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractAGUOffsetScale_HL_LB_PO() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_HL_LB_PO() => AddressUpdateModebegin return AddressUpdate_PostIndex;end;
pure func InstructionContractAGUSignedLoad_HL_LB_PO() => booleanbegin return TRUE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_HL_LB_PO() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1"],"block":[],"catalog_indices":[142],"catalog_records":[{"agu":{"action":"Load","address_kind":"Register","offset_scale":0,"prefetch_returns_address":false,"signed_load":true,"size_bytes":1,"update_mode":"PostIndex"},"asm":"hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f07ff","match":"0x00000009003e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst0","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"RegDst1","pieces":[{"instruction_lsb":11,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcRType","pieces":[{"instruction_lsb":41,"value_lsb":0,"width":2}],"signedness":"encoding-defined","width":2},{"name":"shamt","pieces":[{"instruction_lsb":43,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"hl_lb_po_48_5c7f5c82b186","length_bits":48,"mnemonic":"HL.LB.PO","semantic_family":"AGU","semantic_group":"LDA/POST_INDEX","semantic_handler":"ExecuteScalarLoad","semantic_summary":"HL.LB.PO snapshots its scalar sources, forms its encoded address, and loads one aligned little-endian 1-byte value.","status":"accepted"}],"classification":["agu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1"],"defaults":["Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission.","SrcRType=0 leaves SrcR unchanged, SrcRType=1 sign-extends SrcR[31:0], SrcRType=2 zero-extends SrcR[31:0], and SrcRType=3 negates the full PTO_XLEN value. Encoded shamt zero performs no shift."],"encoding_class":"standalone-encoded","examples":["hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1"],"exceptions":["A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.","A misaligned 1-byte address raises Fault_DataAlignment before translation or permission. A later permission or bounded-memory failure raises Fault_DataPage at the original address.","A fault emits no successful memory event, performs no partial memory or destination effect, preserves pending writeback, and leaves TPC at the faulting instruction.","Recovery performs a full reissue: every address, source snapshot, preflight, memory operation, and destination is recomputed with no retained progress."],"field_contracts":{},"field_zero_meanings":{"RegDst0":"Encoded zero discards this result without suppressing the instruction's other effects.","RegDst1":"Encoded zero discards this result without suppressing the instruction's other effects.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","SrcRType":"Encoded zero leaves the complete PTO_XLEN register-offset value unchanged.","shamt":"Encoded zero performs no shift."},"legality":["Every encoded Reg5 source uses the complete domain: codes 0..23 select absolute GPRs, codes 24..27 select T#1..T#4, and codes 28..31 select U#1..U#4 without consumption.","Every Reg5 destination is assigned: codes 1..23 write GPRs, code 30 pushes U, code 31 pushes T, and codes 0 and 24..29 discard only that result.","All four SrcRType values and all shamt values 0..31 are assigned; apply the modifier before the shift.","Each memory address must be aligned to the 1-byte access size; a 1-byte access is the complete transfer unit."],"memory_effects":["After complete preflight, perform one little-endian 1-byte load and record one relaxed load event.","The load preserves memory and reservation state."],"operands":[{"field":"RegDst0","role":"Reg5 first loaded-value destination or discard"},{"field":"RegDst1","role":"Reg5 updated-base destination or discard"},{"field":"SrcL","role":"Reg5 address-base source"},{"field":"SrcR","role":"Reg5 register-offset source"},{"field":"SrcRType","role":"register-offset transformation selector"},{"field":"shamt","role":"post-transformation logical-left-shift amount"}],"ordering":["Snapshot all explicit and implicit scalar sources before destination or memory effects; duplicate and source/destination aliases observe pre-instruction values.","Complete the relaxed 1-byte memory operation, publish any result or writeback, and then advance TPC."],"standalone_opcode":true,"state_effects":["Form offset = LSL(Modify(SrcR, SrcRType), the encoded shamt) and add it modulo 2^PTO_XLEN to the SrcL base.","Post-index mode accesses the original base and publishes base plus offset only after successful memory completion.","After a successful 1-byte load, sign-extend the loaded value to PTO_XLEN and publish it through the destination.","Successful execution advances TPC by 6 bytes; a rejected or faulting attempt does not retire."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-LB-PO","mnemonic":"HL.LB.PO","summary":"HL.LB.PO snapshots its scalar sources, forms its encoded address, and loads one aligned little-endian 1-byte value.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_LB_PO() => ScalarOperationbegin return ScalarOperation_HL_LB_PO;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_LB_PO() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarLoad;end;
pure func InstructionContractAGUAction_HL_LB_PO() => ScalarAGUActionbegin return ScalarAGU_Load;end;
pure func InstructionContractAGUAddressKind_HL_LB_PO() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_HL_LB_PO() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractAGUOffsetScale_HL_LB_PO() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_HL_LB_PO() => AddressUpdateModebegin return AddressUpdate_PostIndex;end;
pure func InstructionContractAGUSignedLoad_HL_LB_PO() => booleanbegin return TRUE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_HL_LB_PO() => booleanbegin return FALSE;end;// DOC-END: operation
HL.LB.PO is a standalone 48-bit scalar AGU instruction that loads one 1-byte little-endian value and sign-extends the transferred bits when the result is narrower than PTO_XLEN using Register addressing.
The register-offset path applies the encoded SrcRType transformation to SrcR, shifts that result left by shamt, and adds it to the snapshotted SrcL value modulo 2^PTO_XLEN.
After complete preflight, one aligned little-endian 1-byte load is performed. Its result is sign-extended before destination publication.
Post-index mode accesses the original base and publishes base plus offset only after the memory operation succeeds.
RegDst0 is a 5-bit field selecting the first loaded-value result.RegDst1 is a 5-bit field selecting the updated-base result.SrcL is a 5-bit field selecting the address base.SrcR is a 5-bit field selecting the register offset.SrcRType is a 2-bit field selecting the register-offset transformation.shamt is a 5-bit field selecting the post-transformation left shift.All explicit and implicit scalar sources are snapshotted before any memory or destination effect, so aliases use pre-instruction values.
Successful execution records one relaxed load event; memory and reservation state are preserved.
After all result or writeback publication, HL.LB.PO advances TPC by 6 bytes; a rejected or faulting attempt does not retire.
Each accessed address is aligned to the 1-byte transfer unit. Misalignment selects Fault_DataAlignment before translation; a later permission or bounded-memory failure selects Fault_DataPage at the original address.
A fixed-bit mismatch, reserved field value, or unavailable selected T/U source selects Fault_IllegalInstruction before instruction effects.
A fault records no successful memory event and commits no partial memory, result, or writeback effect. Re-execution recomputes the source snapshots, address, preflight, transfer, and publication from the beginning.
This walkthrough explains how to use the page and does not add instruction behavior.
hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 and identify the encoded address fields.Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
No NDF clause is attached to this unit.
12 matching entries
PTO-AVS-AGU-HL-LB-PO-ALIAS-001tests/asl/scalar/agu/HL.LB.PO/scalar-exec-hl-lb-po-registers-001.aslddafc2eeafaf8c48308133368c59293f76c88b35a9cd53ff576e197d93c289d1PTO-AVS-AGU-HL-LB-PO-BOUND-001tests/asl/scalar/agu/HL.LB.PO/scalar-bound-hl-lb-po-address-001.asl37c5ee18c2ba21051b2f71f0a87d3f99414739c145d7336f2cf4048667b8c3b8PTO-AVS-AGU-HL-LB-PO-EXEC-001tests/asl/scalar/agu/HL.LB.PO/scalar-exec-hl-lb-po-direct-001.aslfca187d26a0301427783ce11b8a3755afcbae405c5ccf25a4e21a51ec0bb795aPTO-AVS-AGU-HL-LB-PO-FAULT-001tests/asl/scalar/agu/HL.LB.PO/scalar-fault-hl-lb-po-precise-001.asl74cd4afbb60deac976492281902ea663a4533bf99f0f4abe564b434667898f3fPTO-AVS-SCALAR-HL-LB-PO-DECODE-001tests/asl/scalar/agu/HL.LB.PO/scalar-decode-hl-lb-po-canonical-001.asl1ffb88ae231c9a313aad239ab496c5e7682f3ebb7e4315b2b0a1fc8772781f4ePTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0029…
ADR-0029docs/status/decisions/0029-scalar-agu-totality-and-restart.md778e7bc53a5ae6487c051d66d0f84b6d697d6302628716bf5c745166ce982eefLoading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"agu"
],
"documentation": "docs/scalar/agu/HL.LB.PO.md",
"id": "PTO-SCALAR-HL-LB-PO",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.LB.PO",
"ndf_clause": "PTO-INST-SCALAR-HL-LB-PO"
},
"mnemonic": "HL.LB.PO",
"readiness_subjects": [
"ADR-0029",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-AGU-HL-LB-PO-ALIAS-001",
"PTO-AVS-AGU-HL-LB-PO-BOUND-001",
"PTO-AVS-AGU-HL-LB-PO-EXEC-001",
"PTO-AVS-AGU-HL-LB-PO-FAULT-001"
],
"source": "asl/scalar/agu/HL.LB.PO.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-AGU-HL-LB-PO-ALIAS-001",
"PTO-AVS-AGU-HL-LB-PO-BOUND-001",
"PTO-AVS-AGU-HL-LB-PO-EXEC-001",
"PTO-AVS-AGU-HL-LB-PO-FAULT-001",
"PTO-AVS-SCALAR-HL-LB-PO-DECODE-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd86812a062c337a475f2a416942a21c8536b97a4d589de90041927e3d4216b6b76af8760001d21658e97f5e5c726e4eb0e282bc2e0484d27380c2dcb3033b0f95867b3asl/scalar/agu/HL.LB.PO.aslasl/scalar/agu/HL.LB.PO.asl