HL.LWUIP

assembly

[
  "hl.lwuip [SrcL, simm], ->Dst0, Dst1"
]

block

[]

catalog_indices

[
  217
]

catalog_records

[
  {
    "agu": {
      "action": "LoadPair",
      "address_kind": "Immediate",
      "offset_scale": 2,
      "prefetch_returns_address": false,
      "signed_load": false,
      "size_bytes": 4,
      "update_mode": "None"
    },
    "asm": "hl.lwuip [SrcL, simm], ->Dst0, Dst1",
    "constraints": [],
    "encoding": [
      {
        "index": 0,
        "mask": "0x0000707f003f",
        "match": "0x00006019001e",
        "width_bits": 48
      }
    ],
    "encoding_kind": "HL48",
    "fields": [
      {
        "name": "RegDst0",
        "pieces": [
          {
            "instruction_lsb": 23,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "RegDst1",
        "pieces": [
          {
            "instruction_lsb": 11,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcL",
        "pieces": [
          {
            "instruction_lsb": 31,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "simm17",
        "pieces": [
          {
            "instruction_lsb": 36,
            "value_lsb": 0,
            "width": 12
          },
          {
            "instruction_lsb": 6,
            "value_lsb": 12,
            "width": 5
          }
        ],
        "signedness": "signed",
        "width": 17
      }
    ],
    "form_id": "hl_lwuip_48_2a5d6d8f3b70",
    "length_bits": 48,
    "mnemonic": "HL.LWUIP",
    "semantic_family": "AGU",
    "semantic_group": "LDA/PAIR",
    "semantic_handler": "ExecuteScalarLoadPair",
    "semantic_summary": "HL.LWUIP snapshots its scalar sources, forms its encoded address, and loads two adjacent aligned little-endian 4-byte values.",
    "status": "accepted"
  }
]

classification

[
  "agu"
]

contract

{
  "block_composition": [
    "none"
  ],
  "canonical_assembly": [
    "hl.lwuip [SrcL, simm], ->Dst0, Dst1"
  ],
  "defaults": [
    "Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "hl.lwuip [SrcL, simm], ->Dst0, Dst1"
  ],
  "exceptions": [
    "A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.",
    "A misaligned 4-byte address raises Fault_DataAlignment before translation or permission. A later permission or bounded-memory failure raises Fault_DataPage at the original address.",
    "A fault emits no successful memory event, performs no partial memory or destination effect, preserves pending writeback, and leaves TPC at the faulting instruction.",
    "Recovery performs a full reissue: every address, source snapshot, preflight, memory operation, and destination is recomputed with no retained progress."
  ],
  "field_contracts": {},
  "field_zero_meanings": {
    "RegDst0": "Encoded zero discards this result without suppressing the instruction's other effects.",
    "RegDst1": "Encoded zero discards this result without suppressing the instruction's other effects.",
    "SrcL": "Encoded zero reads the architectural zero GPR.",
    "simm17": "Encoded zero supplies a zero displacement; it does not denote omission."
  },
  "legality": [
    "Every encoded Reg5 source uses the complete domain: codes 0..23 select absolute GPRs, codes 24..27 select T#1..T#4, and codes 28..31 select U#1..U#4 without consumption.",
    "Every Reg5 destination is assigned: codes 1..23 write GPRs, code 30 pushes U, code 31 pushes T, and codes 0 and 24..29 discard only that result.",
    "simm17 assigns every signed 17-bit value -65536..65535; the encoded byte displacement is that value multiplied by 4.",
    "Each memory address must be aligned to the 4-byte access size; a 4-byte access is the complete transfer unit."
  ],
  "memory_effects": [
    "Preflight both adjacent 4-byte addresses before either load; on success record two relaxed load events in address order."
  ],
  "operands": [
    {
      "field": "RegDst0",
      "role": "Reg5 first loaded-value destination or discard"
    },
    {
      "field": "RegDst1",
      "role": "Reg5 second loaded-value destination or discard"
    },
    {
      "field": "SrcL",
      "role": "Reg5 address-base source"
    },
    {
      "field": "simm17",
      "role": "signed address displacement"
    }
  ],
  "ordering": [
    "Snapshot all explicit and implicit scalar sources before destination or memory effects; duplicate and source/destination aliases observe pre-instruction values.",
    "Preflight both addresses, commit the two relaxed 4-byte operations in address order, publish ordered results if any, then advance TPC."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "Sign-extend simm17, multiply it by 4, and add it modulo 2^PTO_XLEN to the SrcL base.",
    "The pair addresses are address and address plus 4; the instruction performs no base writeback.",
    "After both 4-byte probes succeed, zero-extend each result at PTO_XLEN and publish first then second.",
    "Successful execution advances TPC by 6 bytes; a rejected or faulting attempt does not retire."
  ]
}

depends_on

[
  "PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"
]

id

PTO-SCALAR-HL-LWUIP

mnemonic

HL.LWUIP

summary

HL.LWUIP snapshots its scalar sources, forms its encoded address, and loads two adjacent aligned little-endian 4-byte values.

surface

scalar

{
  "classification": [
    "agu"
  ],
  "documentation": "docs/scalar/agu/HL.LWUIP.md",
  "id": "PTO-SCALAR-HL-LWUIP",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "HL.LWUIP",
    "ndf_clause": "PTO-INST-SCALAR-HL-LWUIP"
  },
  "mnemonic": "HL.LWUIP",
  "readiness_subjects": [
    "ADR-0029",
    "ADR-0059"
  ],
  "semantic_tests": [
    "PTO-AVS-AGU-HL-LWUIP-ALIAS-001",
    "PTO-AVS-AGU-HL-LWUIP-BOUND-001",
    "PTO-AVS-AGU-HL-LWUIP-EXEC-001",
    "PTO-AVS-AGU-HL-LWUIP-FAULT-001"
  ],
  "source": "asl/scalar/agu/HL.LWUIP.asl",
  "surface": "scalar",
  "tests": [
    "PTO-AVS-AGU-HL-LWUIP-ALIAS-001",
    "PTO-AVS-AGU-HL-LWUIP-BOUND-001",
    "PTO-AVS-AGU-HL-LWUIP-EXEC-001",
    "PTO-AVS-AGU-HL-LWUIP-FAULT-001",
    "PTO-AVS-SCALAR-HL-LWUIP-DECODE-001"
  ]
}