Operands and parameters
RegDst- Reg5 updated-base destination or discard
SrcD- Reg5 first store-data source
SrcL- Reg5 address-base source
SrcR- Reg5 register-offset source
SrcRType- register-offset transformation selector
HL.SW.UPR snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 4-byte value.
PTO-SCALAR-HL-SW-UPRhl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 updated-base destination or discard | Encoded zero discards this result without suppressing the instruction's other effects. |
SrcD | 5 | encoding-defined | Reg5 first store-data source | Encoded zero reads the architectural zero GPR. |
SrcL | 5 | encoding-defined | Reg5 address-base source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | Reg5 register-offset source | Encoded zero reads the architectural zero GPR. |
SrcRType | 2 | encoding-defined | register-offset transformation selector | Encoded zero leaves the complete PTO_XLEN register-offset value unchanged. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| SrcD | 47:43 | variable |
| SrcRType | 42:41 | variable |
| SrcR | 40:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:16 | 15'b110000001001001 |
| RegDst | 15:11 | variable |
| Constant | 10:0 | 11'b00000101110 |
{
"reg": [
{
"bits": 11,
"name": "11'b00000101110"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 15,
"name": "15'b110000001001001"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "SrcRType"
},
{
"bits": 5,
"name": "SrcD"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}
RegDstSrcDSrcLSrcRSrcRTypeThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_HL_SW_UPR() => ScalarOperationbegin return ScalarOperation_HL_SW_UPR;end;readonly func InstructionContractHandler_HL_SW_UPR() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarStore;end;
pure func InstructionContractAGUAction_HL_SW_UPR() => ScalarAGUActionbegin return ScalarAGU_Store;end;
pure func InstructionContractAGUAddressKind_HL_SW_UPR() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_HL_SW_UPR() => integer {1,2,4,8}begin return 4;end;
pure func InstructionContractAGUOffsetScale_HL_SW_UPR() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_HL_SW_UPR() => AddressUpdateModebegin return AddressUpdate_PreIndex;end;
pure func InstructionContractAGUSignedLoad_HL_SW_UPR() => booleanbegin return FALSE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_HL_SW_UPR() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}"],"block":[],"catalog_indices":[291],"catalog_records":[{"agu":{"action":"Store","address_kind":"Register","offset_scale":0,"prefetch_returns_address":false,"signed_load":false,"size_bytes":4,"update_mode":"PreIndex"},"asm":"hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x00007fff07ff","match":"0x00006049002e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":11,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcD","pieces":[{"instruction_lsb":43,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcRType","pieces":[{"instruction_lsb":41,"value_lsb":0,"width":2}],"signedness":"encoding-defined","width":2}],"form_id":"hl_sw_upr_48_d4ccb513944a","length_bits":48,"mnemonic":"HL.SW.UPR","semantic_family":"AGU","semantic_group":"STA/PRE_INDEX","semantic_handler":"ExecuteScalarStore","semantic_summary":"HL.SW.UPR snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 4-byte value.","status":"accepted"}],"classification":["agu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}"],"defaults":["Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission.","SrcRType=0 leaves SrcR unchanged, SrcRType=1 sign-extends SrcR[31:0], SrcRType=2 zero-extends SrcR[31:0], and SrcRType=3 negates the full PTO_XLEN value. Encoded shamt zero performs no shift."],"encoding_class":"standalone-encoded","examples":["hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}"],"exceptions":["A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.","A misaligned 4-byte address raises Fault_DataAlignment before translation or permission. A later permission or bounded-memory failure raises Fault_DataPage at the original address.","A fault emits no successful memory event, performs no partial memory or destination effect, preserves pending writeback, and leaves TPC at the faulting instruction.","Recovery performs a full reissue: every address, source snapshot, preflight, memory operation, and destination is recomputed with no retained progress."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards this result without suppressing the instruction's other effects.","SrcD":"Encoded zero reads the architectural zero GPR.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","SrcRType":"Encoded zero leaves the complete PTO_XLEN register-offset value unchanged."},"legality":["Every encoded Reg5 source uses the complete domain: codes 0..23 select absolute GPRs, codes 24..27 select T#1..T#4, and codes 28..31 select U#1..U#4 without consumption.","Every Reg5 destination is assigned: codes 1..23 write GPRs, code 30 pushes U, code 31 pushes T, and codes 0 and 24..29 discard only that result.","All four SrcRType values and all shamt values 0..31 are assigned; apply the modifier before the shift.","Each memory address must be aligned to the 4-byte access size; a 4-byte access is the complete transfer unit."],"memory_effects":["After complete preflight, perform one little-endian 4-byte store and record one relaxed store event.","A successful overlapping store invalidates the overlapping reservation; a nonoverlapping reservation remains valid."],"operands":[{"field":"RegDst","role":"Reg5 updated-base destination or discard"},{"field":"SrcD","role":"Reg5 first store-data source"},{"field":"SrcL","role":"Reg5 address-base source"},{"field":"SrcR","role":"Reg5 register-offset source"},{"field":"SrcRType","role":"register-offset transformation selector"}],"ordering":["Snapshot all explicit and implicit scalar sources before destination or memory effects; duplicate and source/destination aliases observe pre-instruction values.","Complete the relaxed 4-byte memory operation, publish any result or writeback, and then advance TPC."],"standalone_opcode":true,"state_effects":["Form offset = LSL(Modify(SrcR, SrcRType), 0) and add it modulo 2^PTO_XLEN to the SrcL base.","Pre-index mode accesses the updated base and publishes that same updated base only after successful memory completion.","Snapshot every store-data source before any memory effect or destination publication.","Successful execution advances TPC by 6 bytes; a rejected or faulting attempt does not retire."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-SW-UPR","mnemonic":"HL.SW.UPR","summary":"HL.SW.UPR snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 4-byte value.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-HL-SW-UPR-DECISION-BINDING-001// ndf: kind=contract level=L1 layer=scalar status=accepted// HL.SW.UPR MUST implement the mnemonic-local canonical assembly, encoded// legality, defaults, state and memory effects, ordering, and fault boundaries// declared in this owner. The operation region below is the executable binding// for every accepted decision that names this mnemonic.// NDF-END: PTO-HL-SW-UPR-DECISION-BINDING-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_SW_UPR() => ScalarOperationbegin return ScalarOperation_HL_SW_UPR;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_SW_UPR() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarStore;end;
pure func InstructionContractAGUAction_HL_SW_UPR() => ScalarAGUActionbegin return ScalarAGU_Store;end;
pure func InstructionContractAGUAddressKind_HL_SW_UPR() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_HL_SW_UPR() => integer {1,2,4,8}begin return 4;end;
pure func InstructionContractAGUOffsetScale_HL_SW_UPR() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_HL_SW_UPR() => AddressUpdateModebegin return AddressUpdate_PreIndex;end;
pure func InstructionContractAGUSignedLoad_HL_SW_UPR() => booleanbegin return FALSE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_HL_SW_UPR() => booleanbegin return FALSE;end;// DOC-END: operation
HL.SW.UPR is a standalone 48-bit AGU instruction that forms a register-offset address and stores one aligned little-endian 4-byte value.
HL.SW.UPR transforms SrcR according to SrcRType and adds the unscaled result modulo 2^PTO_XLEN to the snapshotted SrcL base.
After complete preflight, the instruction performs one little-endian 4-byte store from its snapshotted store-data source.
Pre-index mode accesses the updated base and publishes that same updated base only after successful memory completion.
SrcL supplies the base; SrcR supplies the offset; SrcRType supplies the offset transformation. Every encoded Reg5 source among SrcD, SrcL, SrcR uses codes 0..23 for GPRs, 24..27 for T#1..T#4, and 28..31 for U#1..U#4 without consumption.SrcD supplies store data; RegDst receives the updated base; destination codes 1..23 write GPRs, 30 pushes U, 31 pushes T, and 0 plus 24..29 discard only that result.SrcRType values 0..3 are assigned; the selected transformation is applied before the form's fixed scaling.All explicit and implicit scalar sources are snapshotted before memory or destination effects, so aliases observe pre-instruction values.
A successful attempt records one relaxed store event, invalidates an overlapping reservation but preserves a nonoverlapping one, and advances TPC by 6 bytes.
Each effective address must satisfy 4-byte alignment. Misalignment raises Fault_DataAlignment before translation; a later permission or bounded-memory failure raises Fault_DataPage at the original address.
A fault records no successful memory event, performs no partial memory, destination, or writeback effect, preserves pending writeback, and leaves the faulting TPC available for full reissue.
A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.
This example demonstrates the address calculation only; exact behavior remains in the current ASL and instruction contract.
With base 0x100, unchanged offset source 4, and the fixed shift 0, the aligned displacement is 4 and base plus displacement is 0x104. The memory access uses 0x104. If permitted, the instruction stores 4 bytes at that aligned address.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
HL.SW.UPR MUST implement the mnemonic-local canonical assembly, encoded legality, defaults, state and memory effects, ordering, and fault boundaries declared in this owner. The operation region below is the executable binding for every accepted decision that names this mnemonic.
PTO-HL-SW-UPR-DECISION-BINDING-001asl/scalar/agu/HL.SW.UPR.aslce361ebb04c900240e3c6128ed6509d6174eb0fca5a62ff71f668dbc920dd85ade3dc9b364611f44ab640d75ad56b7dc8f599ab14dda4c1f141492b78679ec3b14 matching entries
PTO-AVS-AGU-HL-SW-UPR-ALIAS-001tests/asl/scalar/agu/HL.SW.UPR/scalar-exec-hl-sw-upr-registers-001.aslc7eeb5ac0a77749cd235f53cb399d58530b7b355be7f8983f9555f485537f55aPTO-AVS-AGU-HL-SW-UPR-BOUND-001tests/asl/scalar/agu/HL.SW.UPR/scalar-bound-hl-sw-upr-address-001.asl80bd63f6bf8715970e426e24c8b7e03e5aa10df51c9e8ab101692167be6d1fd0PTO-AVS-AGU-HL-SW-UPR-EXEC-001tests/asl/scalar/agu/HL.SW.UPR/scalar-exec-hl-sw-upr-direct-001.asl457e7140cb96df40a9f906a8bc27ed063c26a5e184b0c3ad927db14620a31c8fPTO-AVS-AGU-HL-SW-UPR-FAULT-001tests/asl/scalar/agu/HL.SW.UPR/scalar-fault-hl-sw-upr-precise-001.aslceab213b8501fbd4712ca17c1453dfc2c27096404c00ff7aa85af20265a454e5PTO-AVS-SCALAR-HL-SW-UPR-DECODE-001tests/asl/scalar/agu/HL.SW.UPR/scalar-decode-hl-sw-upr-canonical-001.aslfb4af643eca20ea72fac1ac3777cb059cd7fcc62019a790db7750347f6d317a4PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0024…
ADR-0024docs/status/decisions/0024-pc-relative-and-unscaled-agu-addressing.md36dc4f1fbe1714d4eb522f69ccca4216e7a233f55a44cc3f03cb36346911445eLoading ADR-0029…
ADR-0029docs/status/decisions/0029-scalar-agu-totality-and-restart.md778e7bc53a5ae6487c051d66d0f84b6d697d6302628716bf5c745166ce982eefLoading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"agu"
],
"documentation": "docs/scalar/agu/HL.SW.UPR.md",
"id": "PTO-SCALAR-HL-SW-UPR",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.SW.UPR",
"ndf_clause": "PTO-INST-SCALAR-HL-SW-UPR"
},
"mnemonic": "HL.SW.UPR",
"readiness_subjects": [
"ADR-0024",
"ADR-0029",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-AGU-HL-SW-UPR-ALIAS-001",
"PTO-AVS-AGU-HL-SW-UPR-BOUND-001",
"PTO-AVS-AGU-HL-SW-UPR-EXEC-001",
"PTO-AVS-AGU-HL-SW-UPR-FAULT-001"
],
"source": "asl/scalar/agu/HL.SW.UPR.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-AGU-HL-SW-UPR-ALIAS-001",
"PTO-AVS-AGU-HL-SW-UPR-BOUND-001",
"PTO-AVS-AGU-HL-SW-UPR-EXEC-001",
"PTO-AVS-AGU-HL-SW-UPR-FAULT-001",
"PTO-AVS-SCALAR-HL-SW-UPR-DECODE-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd86812ce361ebb04c900240e3c6128ed6509d6174eb0fca5a62ff71f668dbc920dd85a70d78e76c886cfeb1c3006b9e920ed68c909317178463af80b2b5de22b4f1fdbasl/scalar/agu/HL.SW.UPR.aslasl/scalar/agu/HL.SW.UPR.aslasl/scalar/agu/HL.SW.UPR.asl