Operands and parameters
SrcD- Reg5 first store-data source
SrcL- Reg5 address-base source
SrcR- Reg5 register-offset source
SrcRType- register-offset transformation selector
SB snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 1-byte value.
PTO-SCALAR-SBsb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
SrcD | 5 | encoding-defined | Reg5 first store-data source | Encoded zero reads the architectural zero GPR. |
SrcL | 5 | encoding-defined | Reg5 address-base source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | Reg5 register-offset source | Encoded zero reads the architectural zero GPR. |
SrcRType | 2 | encoding-defined | register-offset transformation selector | Encoded zero leaves the complete PTO_XLEN register-offset value unchanged. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| SrcD | 31:27 | variable |
| SrcRType | 26:25 | variable |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:0 | 15'b000000001001001 |
{
"reg": [
{
"bits": 15,
"name": "15'b000000001001001"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "SrcRType"
},
{
"bits": 5,
"name": "SrcD"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]
SrcDSrcLSrcRSrcRTypeThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_SB() => ScalarOperationbegin return ScalarOperation_SB;end;readonly func InstructionContractHandler_SB() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarStore;end;
pure func InstructionContractAGUAction_SB() => ScalarAGUActionbegin return ScalarAGU_Store;end;
pure func InstructionContractAGUAddressKind_SB() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_SB() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractAGUOffsetScale_SB() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_SB() => AddressUpdateModebegin return AddressUpdate_None;end;
pure func InstructionContractAGUSignedLoad_SB() => booleanbegin return FALSE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_SB() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]"],"block":[],"catalog_indices":[377],"catalog_records":[{"agu":{"action":"Store","address_kind":"Register","offset_scale":0,"prefetch_returns_address":false,"signed_load":false,"size_bytes":1,"update_mode":"None"},"asm":"sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]","constraints":[],"encoding":[{"index":0,"mask":"0x00007fff","match":"0x00000049","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"SrcD","pieces":[{"instruction_lsb":27,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcRType","pieces":[{"instruction_lsb":25,"value_lsb":0,"width":2}],"signedness":"encoding-defined","width":2}],"form_id":"sb_32_43c106ae3749","length_bits":32,"mnemonic":"SB","semantic_family":"AGU","semantic_group":"STA/BASE_REG","semantic_handler":"ExecuteScalarStore","semantic_summary":"SB snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 1-byte value.","status":"accepted"}],"classification":["agu"],"contract":{"block_composition":["none"],"canonical_assembly":["sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]"],"defaults":["Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission.","SrcRType=0 leaves SrcR unchanged, SrcRType=1 sign-extends SrcR[31:0], SrcRType=2 zero-extends SrcR[31:0], and SrcRType=3 negates the full PTO_XLEN value. Encoded shamt zero performs no shift."],"encoding_class":"standalone-encoded","examples":["sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]"],"exceptions":["A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.","A misaligned 1-byte address raises Fault_DataAlignment before translation or permission. A later permission or bounded-memory failure raises Fault_DataPage at the original address.","A fault emits no successful memory event, performs no partial memory or destination effect, preserves pending writeback, and leaves TPC at the faulting instruction.","Recovery performs a full reissue: every address, source snapshot, preflight, memory operation, and destination is recomputed with no retained progress."],"field_contracts":{},"field_zero_meanings":{"SrcD":"Encoded zero reads the architectural zero GPR.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","SrcRType":"Encoded zero leaves the complete PTO_XLEN register-offset value unchanged."},"legality":["Every encoded Reg5 source uses the complete domain: codes 0..23 select absolute GPRs, codes 24..27 select T#1..T#4, and codes 28..31 select U#1..U#4 without consumption.","All four SrcRType values and all shamt values 0..31 are assigned; apply the modifier before the shift.","Each memory address must be aligned to the 1-byte access size; a 1-byte access is the complete transfer unit."],"memory_effects":["After complete preflight, perform one little-endian 1-byte store and record one relaxed store event.","A successful overlapping store invalidates the overlapping reservation; a nonoverlapping reservation remains valid."],"operands":[{"field":"SrcD","role":"Reg5 first store-data source"},{"field":"SrcL","role":"Reg5 address-base source"},{"field":"SrcR","role":"Reg5 register-offset source"},{"field":"SrcRType","role":"register-offset transformation selector"}],"ordering":["Snapshot all explicit and implicit scalar sources before destination or memory effects; duplicate and source/destination aliases observe pre-instruction values.","Complete the relaxed 1-byte memory operation, publish any result or writeback, and then advance TPC."],"standalone_opcode":true,"state_effects":["Form offset = LSL(Modify(SrcR, SrcRType), 0) and add it modulo 2^PTO_XLEN to the SrcL base.","Snapshot every store-data source before any memory effect or destination publication.","Successful execution advances TPC by 4 bytes; a rejected or faulting attempt does not retire."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-SB","mnemonic":"SB","summary":"SB snapshots its scalar sources, forms its encoded address, and stores one aligned little-endian 1-byte value.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_SB() => ScalarOperationbegin return ScalarOperation_SB;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_SB() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteScalarStore;end;
pure func InstructionContractAGUAction_SB() => ScalarAGUActionbegin return ScalarAGU_Store;end;
pure func InstructionContractAGUAddressKind_SB() => ScalarAGUAddressKindbegin return ScalarAGU_Register;end;
pure func InstructionContractAGUSizeBytes_SB() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractAGUOffsetScale_SB() => integer {0..3}begin return 0;end;
pure func InstructionContractAGUUpdateMode_SB() => AddressUpdateModebegin return AddressUpdate_None;end;
pure func InstructionContractAGUSignedLoad_SB() => booleanbegin return FALSE;end;
pure func InstructionContractAGUPrefetchReturnsAddress_SB() => booleanbegin return FALSE;end;// DOC-END: operation
SB is a standalone 32-bit AGU instruction that forms a register-offset address and stores one aligned little-endian 1-byte value.
SB transforms SrcR according to SrcRType and adds the unscaled result modulo 2^PTO_XLEN to the snapshotted SrcL base.
After complete preflight, the instruction performs one little-endian 1-byte store from its snapshotted store-data source.
This form performs no base-register writeback; its effective address is used only by the selected memory operation.
SrcL supplies the base; SrcR supplies the offset; SrcRType supplies the offset transformation. Every encoded Reg5 source among SrcD, SrcL, SrcR uses codes 0..23 for GPRs, 24..27 for T#1..T#4, and 28..31 for U#1..U#4 without consumption.SrcD supplies store data.SrcRType values 0..3 are assigned; the selected transformation is applied before the form's fixed scaling.All explicit and implicit scalar sources are snapshotted before memory or destination effects, so aliases observe pre-instruction values.
A successful attempt records one relaxed store event, invalidates an overlapping reservation but preserves a nonoverlapping one, and advances TPC by 4 bytes.
Each effective address must satisfy 1-byte alignment. Misalignment raises Fault_DataAlignment before translation; a later permission or bounded-memory failure raises Fault_DataPage at the original address.
A fault records no successful memory event, performs no partial memory, destination, or writeback effect, preserves pending writeback, and leaves the faulting TPC available for full reissue.
A fixed-bit mismatch, reserved field value, or unavailable selected T/U source raises Fault_IllegalInstruction before instruction effects.
This example demonstrates the address calculation only; exact behavior remains in the current ASL and instruction contract.
With base 0x100, unchanged offset source 2, and the fixed shift 0, the offset is 2 and base plus offset is 0x102. The memory access uses 0x102. If aligned and permitted, the instruction stores 1 byte at that address.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
No NDF clause is attached to this unit.
12 matching entries
PTO-AVS-AGU-SB-ALIAS-001tests/asl/scalar/agu/SB/scalar-exec-sb-registers-001.asl3b32cc2f585bba631690b046d1fbc73b199be9326b06dbcab2425888d49b9cfdPTO-AVS-AGU-SB-BOUND-001tests/asl/scalar/agu/SB/scalar-bound-sb-address-001.asl1d1e2dd55f0a95adea1798b37ef81e8226836b6f4d13f7fe76cd399c0398f952PTO-AVS-AGU-SB-EXEC-001tests/asl/scalar/agu/SB/scalar-exec-sb-direct-001.asla41c9ce1985180505355836cac04a15658d055b40abfd6544c12870fa32b85e5PTO-AVS-AGU-SB-FAULT-001tests/asl/scalar/agu/SB/scalar-fault-sb-precise-001.aslc0c8528a0a02727764aa12c9c90cde6aad1b537e967bfd7e7c5c65c02aa76a05PTO-AVS-SCALAR-SB-DECODE-001tests/asl/scalar/agu/SB/scalar-decode-sb-canonical-001.asl66430455da65a58cd36178dbba0c231fdcaed2fe5351789cace52bf83a4b3ceePTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0029…
ADR-0029docs/status/decisions/0029-scalar-agu-totality-and-restart.md778e7bc53a5ae6487c051d66d0f84b6d697d6302628716bf5c745166ce982eefLoading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"agu"
],
"documentation": "docs/scalar/agu/SB.md",
"id": "PTO-SCALAR-SB",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "SB",
"ndf_clause": "PTO-INST-SCALAR-SB"
},
"mnemonic": "SB",
"readiness_subjects": [
"ADR-0029",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-AGU-SB-ALIAS-001",
"PTO-AVS-AGU-SB-BOUND-001",
"PTO-AVS-AGU-SB-EXEC-001",
"PTO-AVS-AGU-SB-FAULT-001"
],
"source": "asl/scalar/agu/SB.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-AGU-SB-ALIAS-001",
"PTO-AVS-AGU-SB-BOUND-001",
"PTO-AVS-AGU-SB-EXEC-001",
"PTO-AVS-AGU-SB-FAULT-001",
"PTO-AVS-SCALAR-SB-DECODE-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd868122bf7c3fafacc891d00dbfbf84b1f363c278844c7e5b5d95b075fa02be81448293374a9d545d02892d2712aadca562387dad62cf50f44b9e7f5b9a283c4c813baasl/scalar/agu/SB.aslasl/scalar/agu/SB.asl