Operands and parameters
RegDst- Reg5 scalar destination or discard selector
SrcL- Reg5 scalar source
simm24- signed split 24-bit immediate
HL.ANDI applies XLEN bitwise conjunction to SrcL and a sign-extended 24-bit immediate.
PTO-SCALAR-HL-ANDIhl.andi SrcL, simm, ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 scalar destination or discard selector | Encoded zero discards the result and does not modify any GPR or queue. |
SrcL | 5 | encoding-defined | Reg5 scalar source | Encoded zero reads architectural GPR zero. |
simm24 | 24 | signed | signed split 24-bit immediate | Encoded zero supplies numeric zero. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| simm24 | 47:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:28 | 3'b010 |
| RegDst | 27:23 | variable |
| Constant | 22:16 | 7'b0010101 |
| simm24 | 15:4 | variable |
| Constant | 3:0 | 4'b1110 |
{
"reg": [
{
"bits": 4,
"name": "4'b1110"
},
{
"bits": 12,
"name": "simm24"
},
{
"bits": 7,
"name": "7'b0010101"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b010"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 12,
"name": "simm24"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.andi SrcL, simm, ->{t, u, Rd}
RegDstSrcLsimm24This Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_HL_ANDI() => ScalarOperationbegin return ScalarOperation_HL_ANDI;end;readonly func InstructionContractHandler_HL_ANDI() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractImmediateWidth_HL_ANDI() => integer {1..64}begin return 24;end;
pure func InstructionContractImmediateIsSigned_HL_ANDI() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_HL_ANDI() => booleanbegin return FALSE;end;
pure func InstructionContractResult_HL_ANDI( left: Word, immediate: bits(24)) => Wordbegin let right = SignExtend{PTO_XLEN}(immediate); return ScalarBinary( ScalarBinary_AND, left, right);end;// PTO-INSTRUCTION: {"assembly":["hl.andi SrcL, simm, ->{t, u, Rd}"],"block":[],"catalog_indices":[120],"catalog_records":[{"asm":"hl.andi SrcL, simm, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f000f","match":"0x00002015000e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"simm24","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":12},{"instruction_lsb":4,"value_lsb":12,"width":12}],"signedness":"signed","width":24}],"form_id":"hl_andi_48_fe11c7ebca41","length_bits":48,"mnemonic":"HL.ANDI","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinary","semantic_summary":"HL.ANDI applies XLEN bitwise conjunction to SrcL and a sign-extended 24-bit immediate.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.andi SrcL, simm, ->{t, u, Rd}"],"defaults":["SrcL, simm24, and RegDst are required encoded fields; no field can be omitted.","simm24 has the complete signed 24-bit range -8388608 through 8388607; encoded zero is numeric zero."],"encoding_class":"standalone-encoded","examples":["hl.andi a0, -1, ->a0","hl.andi t#1, -8388608, ->u","hl.andi zero, 8388607, ->zero"],"exceptions":["HL.ANDI raises no arithmetic exception; fixed-width overflow or underflow is discarded.","A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before any destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result and does not modify any GPR or queue.","SrcL":"Encoded zero reads architectural GPR zero.","simm24":"Encoded zero supplies numeric zero."},"legality":["All 32 SrcL encodings are assigned: 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consuming a queue entry.","All 32 RegDst encodings are assigned: codes 0 and 24..29 discard, codes 1..23 write absolute GPRs, code 30 pushes U, and code 31 pushes T.","Every signed 24-bit two's-complement value is assigned. The two 12-bit pieces reconstruct one exact 24-bit value."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 scalar destination or discard selector"},{"field":"SrcL","role":"Reg5 scalar source"},{"field":"simm24","role":"signed split 24-bit immediate"}],"ordering":["Snapshot SrcL before the destination effect, including GPR aliases and same-queue read-then-push cases.","Publish the result through RegDst, then advance TPC by six bytes."],"standalone_opcode":true,"state_effects":["Sign-extend simm24 to PTO_XLEN, compute bitwise conjunction with the snapshotted SrcL value modulo 2^PTO_XLEN where applicable, and publish the result through RegDst.","Codes 1..23 write a GPR; codes 0 and 24..29 discard; code 30 pushes U; code 31 pushes T. Relative source reads are non-consuming.","No memory, reservation, descriptor, Tile, block, privilege, numeric-status, branch-target, or other control state changes. Successful execution advances TPC by six bytes."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-ANDI","mnemonic":"HL.ANDI","summary":"HL.ANDI applies XLEN bitwise conjunction to SrcL and a sign-extended 24-bit immediate.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-HL-ANDI-CONTRACT-001// ndf: kind=contract level=L1 layer=scalar status=accepted// HL.ANDI MUST reconstruct its split simm24 field exactly and apply// bitwise conjunction with a sign-extended signed 24-bit immediate.// The result MUST wrap modulo 2^PTO_XLEN.// SrcL MUST use the complete non-consuming Reg5 source map. RegDst MUST// use the common GPR, discard, U-push, and T-push destination map.// The source MUST be snapshotted before destination publication.// Successful execution MUST advance TPC by six bytes and MUST NOT change// memory, Tile, block, reservation, privilege, numeric-status, or fault state.// NDF-END: PTO-HL-ANDI-CONTRACT-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_ANDI() => ScalarOperationbegin return ScalarOperation_HL_ANDI;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_ANDI() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractImmediateWidth_HL_ANDI() => integer {1..64}begin return 24;end;
pure func InstructionContractImmediateIsSigned_HL_ANDI() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_HL_ANDI() => booleanbegin return FALSE;end;
pure func InstructionContractResult_HL_ANDI( left: Word, immediate: bits(24)) => Wordbegin let right = SignExtend{PTO_XLEN}(immediate); return ScalarBinary( ScalarBinary_AND, left, right);end;// DOC-END: operation
HL.ANDI is a 48-bit scalar ALU instruction. It performs bitwise conjunction under the complete XLEN value result rules; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then performs bitwise conjunction under the complete XLEN value result rules, and only afterward performs the destination effects.
RegDst field selects the Reg5 scalar result target or discards the result.SrcL field selects a scalar value through Reg5.simm24 field carries the signed split 24-bit immediate.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
Every scalar source is snapshotted before the destination effect. The completed value is then routed through RegDst using the current scalar destination map.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 6 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
Fixed-width arithmetic follows the operation’s wraparound rule without an arithmetic exception. A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before publication and before TPC advances.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small HL.ANDI example, SrcL=0xc and simm24=0xa produce 0x8.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
HL.ANDI MUST reconstruct its split simm24 field exactly and apply bitwise conjunction with a sign-extended signed 24-bit immediate. The result MUST wrap modulo 2^PTO_XLEN. SrcL MUST use the complete non-consuming Reg5 source map. RegDst MUST use the common GPR, discard, U-push, and T-push destination map. The source MUST be snapshotted before destination publication. Successful execution MUST advance TPC by six bytes and MUST NOT change memory, Tile, block, reservation, privilege, numeric-status, or fault state.
PTO-HL-ANDI-CONTRACT-001asl/scalar/alu/HL.ANDI.asl76b322aee81b3e003542e79369d3db81d4d86c10ec59458393d1937ef6fcfd038519f4c122a622db4ff48925aa5f398c73812700f6805a805e8ecd51637f005812 matching entries
PTO-AVS-SCALAR-HL-ANDI-DECODE-001tests/asl/scalar/alu/HL.ANDI/scalar-decode-hl-andi-canonical-001.aslf3cb44e5896fc0ff159113f25ade9f6570cf06a82c3f21cab39d7968a8e28a60PTO-AVS-SCALAR-HL-ANDI-READINESS-001tests/asl/scalar/alu/HL.ANDI/scalar-fault-hl-andi-readiness-001.asle1bf1c9e310e8c8eaea2db71025dca5c1347a9e891af51c9a16c14cea173d47aPTO-AVS-SCALAR-HL-ANDI-RESULT-001tests/asl/scalar/alu/HL.ANDI/scalar-exec-hl-andi-result-001.asld81c650bd73c9d070f4bf58f522ff0552fdc1bb2b1021b4ebf2d4c3932414e1fPTO-AVS-SCALAR-HL-ANDI-SELECTORS-001tests/asl/scalar/alu/HL.ANDI/scalar-bound-hl-andi-selectors-001.asle6403c532124ee89fb106003df9d9dc0e3773eb204351579ded0e2115c144ebcPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/HL.ANDI.md",
"id": "PTO-SCALAR-HL-ANDI",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.ANDI",
"ndf_clause": "PTO-INST-SCALAR-HL-ANDI"
},
"mnemonic": "HL.ANDI",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-HL-ANDI-READINESS-001",
"PTO-AVS-SCALAR-HL-ANDI-RESULT-001",
"PTO-AVS-SCALAR-HL-ANDI-SELECTORS-001"
],
"source": "asl/scalar/alu/HL.ANDI.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-HL-ANDI-DECODE-001",
"PTO-AVS-SCALAR-HL-ANDI-READINESS-001",
"PTO-AVS-SCALAR-HL-ANDI-RESULT-001",
"PTO-AVS-SCALAR-HL-ANDI-SELECTORS-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd8681276b322aee81b3e003542e79369d3db81d4d86c10ec59458393d1937ef6fcfd039d2afa3ad51f11fb5f45b3e81ca85cd9b169547e42e23ca4901b7a33c5ca801basl/scalar/alu/HL.ANDI.aslasl/scalar/alu/HL.ANDI.aslasl/scalar/alu/HL.ANDI.asl