HL.CCATW logically right-shifts {SrcL[31:0], SrcR[31:0]}, sign-extends the low then high 32-bit results, and writes them in order.
PTO-SCALAR-HL-CCATWhl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst0 | 5 | encoding-defined | ordered low-result Reg5 destination or discard | Encoded zero discards the low result. |
RegDst1 | 5 | encoding-defined | ordered high-result Reg5 destination or discard | Encoded zero discards the high result. |
SrcL | 5 | encoding-defined | upper low-word Reg5 source | Encoded zero reads architectural GPR zero. |
SrcR | 5 | encoding-defined | lower low-word Reg5 source | Encoded zero reads architectural GPR zero. |
shamt | 7 | encoding-defined | unsigned seven-bit logical-right shift amount | Encoded zero performs no shift. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| shamt | 47:41 | variable |
| SrcR | 40:36 | variable |
| SrcL | 35:31 | variable |
| Constant | 30:28 | 3'b010 |
| RegDst0 | 27:23 | variable |
| Constant | 22:16 | 7'b1011101 |
| RegDst1 | 15:11 | variable |
| Constant | 10:0 | 11'b00000001110 |
{
"reg": [
{
"bits": 11,
"name": "11'b00000001110"
},
{
"bits": 5,
"name": "RegDst1"
},
{
"bits": 7,
"name": "7'b1011101"
},
{
"bits": 5,
"name": "RegDst0"
},
{
"bits": 3,
"name": "3'b010"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 7,
"name": "shamt"
}
],
"config": {
"bits": 48,
"fontsize": 13,
"hspace": 900,
"lanes": 2,
"offset": 0
}
}hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1
RegDst0RegDst1SrcLSrcRshamtThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_HL_CCATW() => ScalarOperationbegin return ScalarOperation_HL_CCATW;end;readonly func InstructionContractHandler_HL_CCATW() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteConcatenatePairW;end;
pure func InstructionContractLowResult_HL_CCATW( left: Word, right: Word, shift_amount: integer {0..127}) => Wordbegin if shift_amount < 64 then var packed: Word = Zeros{PTO_XLEN}; packed[31:0] = right[31:0]; packed[63:32] = left[31:0]; return SignExtend{PTO_XLEN}( LSR(packed, shift_amount)[31:0]); else return Zeros{PTO_XLEN}; end;end;
pure func InstructionContractHighResult_HL_CCATW( left: Word, right: Word, shift_amount: integer {0..127}) => Wordbegin if shift_amount < 64 then var packed: Word = Zeros{PTO_XLEN}; packed[31:0] = right[31:0]; packed[63:32] = left[31:0]; return SignExtend{PTO_XLEN}( LSR(packed, shift_amount)[63:32]); else return Zeros{PTO_XLEN}; end;end;// PTO-INSTRUCTION: {"assembly":["hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1"],"block":[],"catalog_indices":[128],"catalog_records":[{"asm":"hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f07ff","match":"0x0000205d000e","width_bits":48}],"encoding_kind":"HL48","fields":[{"name":"RegDst0","pieces":[{"instruction_lsb":23,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"RegDst1","pieces":[{"instruction_lsb":11,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":31,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":36,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"shamt","pieces":[{"instruction_lsb":41,"value_lsb":0,"width":7}],"signedness":"encoding-defined","width":7}],"form_id":"hl_ccatw_48_24a85ea4659c","length_bits":48,"mnemonic":"HL.CCATW","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ExecuteConcatenatePairW","semantic_summary":"HL.CCATW logically right-shifts {SrcL[31:0], SrcR[31:0]}, sign-extends the low then high 32-bit results, and writes them in order.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1"],"defaults":["SrcL, SrcR, shamt, RegDst0, and RegDst1 are required encoded fields; no field can be omitted.","Encoded shamt zero performs no shift."],"encoding_class":"standalone-encoded","examples":["hl.ccatw a0, a1, 0, ->a2, a3","hl.ccatw t#1, u#1, 64, ->zero, a0","hl.ccatw a0, a1, 127, ->t, t"],"exceptions":["The concatenation shift is total for every shamt and raises no arithmetic exception.","A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before either destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst0":"Encoded zero discards the low result.","RegDst1":"Encoded zero discards the high result.","SrcL":"Encoded zero reads architectural GPR zero.","SrcR":"Encoded zero reads architectural GPR zero.","shamt":"Encoded zero performs no shift."},"legality":["SrcL and SrcR independently use the complete Reg5 source map: GPR0..GPR23, T#1..T#4, and U#1..U#4.","RegDst0 and RegDst1 independently use the common destination map: GPR writes, discard codes, U push, or T push.","shamt 0..127 is fully assigned; values 64..127 produce two zeros."],"memory_effects":["none"],"operands":[{"field":"RegDst0","role":"ordered low-result Reg5 destination or discard"},{"field":"RegDst1","role":"ordered high-result Reg5 destination or discard"},{"field":"SrcL","role":"upper low-word Reg5 source"},{"field":"SrcR","role":"lower low-word Reg5 source"},{"field":"shamt","role":"unsigned seven-bit logical-right shift amount"}],"ordering":["Snapshot both sources before either destination effect; relative source reads do not consume queue entries.","Publish Dst0 first and Dst1 second. Equal GPR destinations retain Dst1; equal queue destinations enqueue Dst0 before Dst1.","After both destination effects, advance TPC by six bytes."],"standalone_opcode":true,"state_effects":["Pack SrcL[31:0] above SrcR[31:0]. For shamt 0..63, logically shift the 64-bit value right, sign-extend result bits 31:0 to Dst0 and bits 63:32 to Dst1; for shamt 64..127 both results are zero.","Apply the complete Reg5 destination map independently in Dst0 then Dst1 order; discard destinations have no effect.","No memory, reservation, descriptor, Tile, block, privilege, numeric-status, branch-target, or other control state changes. Successful execution advances TPC by six bytes."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-HL-CCATW","mnemonic":"HL.CCATW","summary":"HL.CCATW logically right-shifts {SrcL[31:0], SrcR[31:0]}, sign-extends the low then high 32-bit results, and writes them in order.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-HL-CCATW-CONTRACT-001// ndf: kind=contract level=L1 layer=scalar status=accepted// HL.CCATW MUST snapshot SrcL and SrcR, form {SrcL[31:0], SrcR[31:0]}, and// logically shift the concatenation right by the complete seven-bit shamt.// Dst0 MUST receive the low result before Dst1 receives the high result.// Each 32-bit result MUST be sign-extended; shifts 64 through 127 MUST produce two zeros.// Both sources MUST use the complete non-consuming Reg5 source map and// both destinations MUST use the common ordered Reg5 destination map.// Successful execution MUST advance TPC by six bytes and preserve all// memory, Tile, block, reservation, privilege, numeric-status, and fault state.// NDF-END: PTO-HL-CCATW-CONTRACT-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_HL_CCATW() => ScalarOperationbegin return ScalarOperation_HL_CCATW;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_HL_CCATW() => ScalarSemanticHandlerbegin return ScalarHandler_ExecuteConcatenatePairW;end;
pure func InstructionContractLowResult_HL_CCATW( left: Word, right: Word, shift_amount: integer {0..127}) => Wordbegin if shift_amount < 64 then var packed: Word = Zeros{PTO_XLEN}; packed[31:0] = right[31:0]; packed[63:32] = left[31:0]; return SignExtend{PTO_XLEN}( LSR(packed, shift_amount)[31:0]); else return Zeros{PTO_XLEN}; end;end;
pure func InstructionContractHighResult_HL_CCATW( left: Word, right: Word, shift_amount: integer {0..127}) => Wordbegin if shift_amount < 64 then var packed: Word = Zeros{PTO_XLEN}; packed[31:0] = right[31:0]; packed[63:32] = left[31:0]; return SignExtend{PTO_XLEN}( LSR(packed, shift_amount)[63:32]); else return Zeros{PTO_XLEN}; end;end;// DOC-END: operation
HL.CCATW is a 48-bit scalar ALU instruction. It concatenates the two source portions, applies the encoded logical right shift, and separates the result into low and high word destinations; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then concatenates the two source portions, applies the encoded logical right shift, and separates the result into low and high word destinations, and only afterward performs the destination effects.
RegDst0 field selects the first, low-result Reg5 target or discards that result.RegDst1 field selects the second, high-result Reg5 target or discards that result.SrcL field selects the upper concatenation source low word through Reg5.SrcR field selects the lower concatenation source low word through Reg5.shamt field encodes the unsigned seven-bit logical-right shift amount.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
All results are computed before publication. The destinations are then updated in encoded order (RegDst0, RegDst1), which also defines the order of duplicate-register writes or queue pushes.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 6 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
Every encoded concatenation shift is defined and zero-filling. A fixed-bit mismatch or unavailable selected T/U source faults before either destination effect.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small HL.CCATW example, with shift 0, upper source 1, and lower source 2, the ordered low and high results are 2 then 1.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
HL.CCATW MUST snapshot SrcL and SrcR, form {SrcL[31:0], SrcR[31:0]}, and logically shift the concatenation right by the complete seven-bit shamt. Dst0 MUST receive the low result before Dst1 receives the high result. Each 32-bit result MUST be sign-extended; shifts 64 through 127 MUST produce two zeros. Both sources MUST use the complete non-consuming Reg5 source map and both destinations MUST use the common ordered Reg5 destination map. Successful execution MUST advance TPC by six bytes and preserve all memory, Tile, block, reservation, privilege, numeric-status, and fault state.
PTO-HL-CCATW-CONTRACT-001asl/scalar/alu/HL.CCATW.asl1b7768e6a8e4bcdd3c3ed753437689294a614bfae71d7f3669d2e0243f8ddd0835d97c6bf601ece316d8429505cac8bd3884e0ec9f23bb8e6a23d40020a2b87412 matching entries
PTO-AVS-SCALAR-HL-CCATW-DECODE-001tests/asl/scalar/alu/HL.CCATW/scalar-decode-hl-ccatw-canonical-001.asl8eec95cfff700b20a2703e91a6d04c6a28b67050a68e0c54167a6808b794cc02PTO-AVS-SCALAR-HL-CCATW-OVERLAP-001tests/asl/scalar/alu/HL.CCATW/scalar-bound-hl-ccatw-overlap-001.asl1deb8433adc5f32d4e61d48886e035aa1b0497804b3f32179ec0b5f11110ab55PTO-AVS-SCALAR-HL-CCATW-READINESS-001tests/asl/scalar/alu/HL.CCATW/scalar-fault-hl-ccatw-readiness-001.asl9db7259e0008c82a289d07d3edb0f587fe8dce698a3d08795aed9dc60d172a5fPTO-AVS-SCALAR-HL-CCATW-SHIFT-001tests/asl/scalar/alu/HL.CCATW/scalar-exec-hl-ccatw-shift-001.asl4201b7379b09be9e959ba4c639a4e62883c810805f4a5db38feeeeede94a761aPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/HL.CCATW.md",
"id": "PTO-SCALAR-HL-CCATW",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "HL.CCATW",
"ndf_clause": "PTO-INST-SCALAR-HL-CCATW"
},
"mnemonic": "HL.CCATW",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-HL-CCATW-OVERLAP-001",
"PTO-AVS-SCALAR-HL-CCATW-READINESS-001",
"PTO-AVS-SCALAR-HL-CCATW-SHIFT-001"
],
"source": "asl/scalar/alu/HL.CCATW.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-HL-CCATW-DECODE-001",
"PTO-AVS-SCALAR-HL-CCATW-OVERLAP-001",
"PTO-AVS-SCALAR-HL-CCATW-READINESS-001",
"PTO-AVS-SCALAR-HL-CCATW-SHIFT-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd868121b7768e6a8e4bcdd3c3ed753437689294a614bfae71d7f3669d2e0243f8ddd08f0b71174ada7367540232c786ec8e52b2853295366f26985fbfff5714f6a85e4asl/scalar/alu/HL.CCATW.aslasl/scalar/alu/HL.CCATW.aslasl/scalar/alu/HL.CCATW.asl