Operands and parameters
RegDst- Reg5 destination or discard
SrcD- addend Reg5 source
SrcL- left multiplicand or additive Reg5 source
SrcR- right multiplicand Reg5 source
MADD adds a snapshotted XLEN addend to the low XLEN scalar product modulo 2^PTO_XLEN and publishes the result.
PTO-SCALAR-MADDmadd SrcL, SrcR, SrcD, ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 destination or discard | Encoded zero discards the result. |
SrcD | 5 | encoding-defined | addend Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcL | 5 | encoding-defined | left multiplicand or additive Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | right multiplicand Reg5 source | Encoded zero reads the architectural zero GPR. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| SrcD | 31:27 | variable |
| Constant | 26:25 | 2'b00 |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b110 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b1000111 |
{
"reg": [
{
"bits": 7,
"name": "7'b1000111"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b110"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "2'b00"
},
{
"bits": 5,
"name": "SrcD"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}madd SrcL, SrcR, SrcD, ->{t, u, Rd}
RegDstSrcDSrcLSrcRThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_MADD() => ScalarOperationbegin return ScalarOperation_MADD;end;readonly func InstructionContractHandler_MADD() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarMultiplyAdd;end;pure func InstructionContractResult_MADD(addend: Word, left: Word, right: Word) => Wordbegin return ScalarMultiplyAdd(addend, left, right);end;// PTO-INSTRUCTION: {"assembly":["madd SrcL, SrcR, SrcD, ->{t, u, Rd}"],"block":[],"catalog_indices":[356],"catalog_records":[{"asm":"madd SrcL, SrcR, SrcD, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0600707f","match":"0x00006047","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcD","pieces":[{"instruction_lsb":27,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"madd_32_6208e8e59303","length_bits":32,"mnemonic":"MADD","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarMultiplyAdd","semantic_summary":"MADD adds a snapshotted XLEN addend to the low XLEN scalar product modulo 2^PTO_XLEN and publishes the result.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["madd SrcL, SrcR, SrcD, ->{t, u, Rd}"],"defaults":["Every encoded operand and destination field is required; no field can be omitted.","The mnemonic fixes signedness, effective operand width, single-versus-pair result shape, and add-versus-subtract behavior; there is no encoded arithmetic mode."],"encoding_class":"standalone-encoded","examples":["madd srcl, srcr, srcd, ->{t, u, rd}"],"exceptions":["Multiplication and accumulation are fixed-width and raise no arithmetic exception; discarded overflow wraps modulo the defined result width.","An unavailable selected T/U source raises Fault_IllegalInstruction before any destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"SrcD":"Encoded zero reads the architectural zero GPR.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","RegDst":"Encoded zero discards the result."},"legality":["Every source Reg5 code is assigned: 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","Each destination independently uses the common map: codes 0 and 24..29 discard, codes 1..23 write GPRs, code 30 pushes U, and code 31 pushes T.","Fixed encoding bits must match the canonical form; every encoded source, destination, and immediate value otherwise has assigned behavior."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 destination or discard"},{"field":"SrcD","role":"addend Reg5 source"},{"field":"SrcL","role":"left multiplicand or additive Reg5 source"},{"field":"SrcR","role":"right multiplicand Reg5 source"}],"ordering":["Snapshot every source before any destination effect so duplicate selectors and destination aliases observe pre-instruction values.","Publish the result, then advance TPC by four bytes."],"standalone_opcode":true,"state_effects":["Multiply SrcL and SrcR modulo 2^PTO_XLEN, add SrcD modulo 2^PTO_XLEN, and retain the low XLEN bits.","Snapshot every source before the destination effect, publish the XLEN result through the common Reg5 destination map, and do not consume relative sources.","No memory, reservation, descriptor, numeric-status, block, privilege, branch-target, or other control state changes. Successful execution advances TPC by four bytes."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-MADD","mnemonic":"MADD","summary":"MADD adds a snapshotted XLEN addend to the low XLEN scalar product modulo 2^PTO_XLEN and publishes the result.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_MADD() => ScalarOperationbegin return ScalarOperation_MADD;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_MADD() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarMultiplyAdd;end;pure func InstructionContractResult_MADD(addend: Word, left: Word, right: Word) => Wordbegin return ScalarMultiplyAdd(addend, left, right);end;// DOC-END: operation
MADD is a 32-bit scalar ALU instruction. It adds a snapshotted addend to the product under the complete XLEN value arithmetic; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then adds a snapshotted addend to the product under the complete XLEN value arithmetic, and only afterward performs the destination effects.
RegDst field selects the Reg5 result target or discards the result.SrcD field selects the addend through Reg5.SrcL field selects the left multiplicand or additive operand through Reg5.SrcR field selects the right multiplicand through Reg5.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
Every scalar source is snapshotted before the destination effect. The completed value is then routed through RegDst using the current scalar destination map.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 4 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
Fixed-width arithmetic follows the operation’s wraparound rule without an arithmetic exception. A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before publication and before TPC advances.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small MADD example, multiplicands 6 and 7 with addend 1 produce the single result 43.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
No NDF clause is attached to this unit.
9 matching entries
PTO-AVS-SCALAR-MADD-ACCUMULATE-001tests/asl/scalar/alu/MADD/scalar-exec-madd-accumulate-001.aslce12a8a5fce43dac3751b2bd1164286b2e3ab75f8eddf822ed57c864820b0b96PTO-AVS-SCALAR-MADD-DECODE-001tests/asl/scalar/alu/MADD/scalar-decode-madd-canonical-001.asl392d5814d6ede4234bc561960ca138d32d1b51fa61ae9b9c30e2f8a2f167c28cPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/MADD.md",
"id": "PTO-SCALAR-MADD",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "MADD",
"ndf_clause": "PTO-INST-SCALAR-MADD"
},
"mnemonic": "MADD",
"readiness_subjects": [
"ADR-0026",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-SCALAR-MADD-ACCUMULATE-001"
],
"source": "asl/scalar/alu/MADD.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-MADD-ACCUMULATE-001",
"PTO-AVS-SCALAR-MADD-DECODE-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd868124deaaf69a0da571d351f1ff44eccd72faa2aa22406917efb300dd1f7f23feb93c19ba72bd150e4f252a35aef69e0c57ba7fce810bf64b3c7c22f64f20f6ff9abasl/scalar/alu/MADD.aslasl/scalar/alu/MADD.asl