Operands and parameters
RegDst- Reg5 destination or discard
SrcL- left Reg5 source
SrcR- right Reg5 source
MINU performs an unsigned full-XLEN comparison and publishes the complete bit pattern of the minimum operand.
PTO-SCALAR-MINUminu SrcL, SrcR, ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 destination or discard | Encoded zero discards the result. |
SrcL | 5 | encoding-defined | left Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | right Reg5 source | Encoded zero reads the architectural zero GPR. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| Constant | 31:25 | 7'b0000100 |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b101 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b1011011 |
{
"reg": [
{
"bits": 7,
"name": "7'b1011011"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b101"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 7,
"name": "7'b0000100"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}minu SrcL, SrcR, ->{t, u, Rd}
RegDstSrcLSrcRThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_MINU() => ScalarOperationbegin return ScalarOperation_MINU;end;readonly func InstructionContractHandler_MINU() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractResult_MINU(left: Word, right: Word) => Wordbegin if UInt(left) < UInt(right) then return left; else return right; end;end;
pure func InstructionContractUsesSignedComparison_MINU() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["minu SrcL, SrcR, ->{t, u, Rd}"],"block":[],"catalog_indices":[361],"catalog_records":[{"asm":"minu SrcL, SrcR, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0xfe00707f","match":"0x0800505b","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"minu_32_9bdb71ef7b19","length_bits":32,"mnemonic":"MINU","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinary","semantic_summary":"MINU performs an unsigned full-XLEN comparison and publishes the complete bit pattern of the minimum operand.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["minu SrcL, SrcR, ->{t, u, Rd}"],"defaults":["SrcL, SrcR, and RegDst are required fields; no field can be omitted.","Encoded source zero reads the architectural zero GPR; encoded destination zero discards the result."],"encoding_class":"standalone-encoded","examples":["minu a0, a1, ->a2","minu t#1, u#1, ->u","minu zero, zero, ->zero"],"exceptions":["MINU raises no arithmetic exception; comparison selects one unchanged operand bit pattern.","Bits 31:25 are fixed by the accepted form. A mismatch or unavailable T/U source raises Fault_IllegalInstruction before the destination effect and TPC advance."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR."},"legality":["SrcL and SrcR codes 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","RegDst codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs.","The operands use an unsigned full-XLEN comparison; every XLEN bit pattern is legal."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 destination or discard"},{"field":"SrcL","role":"left Reg5 source"},{"field":"SrcR","role":"right Reg5 source"}],"ordering":["Snapshot both sources before the destination effect so repeated sources, destination aliases, and queue publication use pre-instruction values.","Publish the selected operand, then advance TPC by four bytes."],"standalone_opcode":true,"state_effects":["Perform an unsigned full-XLEN comparison and return the complete bit pattern of the minimum operand; equal operands are observationally identical.","Destination codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs; source queues are non-consuming.","No memory, reservation, descriptor, numeric-flag, trap, block, privilege, or control-flow state changes except the successful TPC advance."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-MINU","mnemonic":"MINU","summary":"MINU performs an unsigned full-XLEN comparison and publishes the complete bit pattern of the minimum operand.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_MINU() => ScalarOperationbegin return ScalarOperation_MINU;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_MINU() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractResult_MINU(left: Word, right: Word) => Wordbegin if UInt(left) < UInt(right) then return left; else return right; end;end;
pure func InstructionContractUsesSignedComparison_MINU() => booleanbegin return FALSE;end;// DOC-END: operation
MINU is a 32-bit scalar ALU instruction. It compares the complete operands as unsigned values and selects the minimum bit pattern; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then compares the complete operands as unsigned values and selects the minimum bit pattern, and only afterward performs the destination effects.
RegDst field selects the Reg5 result target or discards the result.SrcL field selects the left operand through Reg5.SrcR field selects the right operand through Reg5.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
Every scalar source is snapshotted before the destination effect. The completed value is then routed through RegDst using the current scalar destination map.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 4 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
Fixed-width arithmetic follows the operation’s wraparound rule without an arithmetic exception. A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before publication and before TPC advances.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small MINU example, operands 7 and 3 select result 3.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
No NDF clause is attached to this unit.
10 matching entries
PTO-AVS-SCALAR-MINU-ALIASES-001tests/asl/scalar/alu/MINU/scalar-bound-minu-aliases-001.asl8c61317bdfbe08e69d9f6da7a983b367e779506b85730291df8567d2f46786b8PTO-AVS-SCALAR-MINU-BOUNDARY-001tests/asl/scalar/alu/MINU/scalar-exec-minu-boundary-001.asl160bccf2ed7c33c49ff763c30bca27c21bdbb9bfd1a9cdb4d080757c97aaeca2PTO-AVS-SCALAR-MINU-DECODE-001tests/asl/scalar/alu/MINU/scalar-decode-minu-canonical-001.asl8e2861262a7dc30296fef9453a1c5d9767440cf1b6f919d111ac687e8b1356d5PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/MINU.md",
"id": "PTO-SCALAR-MINU",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "MINU",
"ndf_clause": "PTO-INST-SCALAR-MINU"
},
"mnemonic": "MINU",
"readiness_subjects": [
"ADR-0026",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-SCALAR-MINU-ALIASES-001",
"PTO-AVS-SCALAR-MINU-BOUNDARY-001"
],
"source": "asl/scalar/alu/MINU.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-MINU-ALIASES-001",
"PTO-AVS-SCALAR-MINU-BOUNDARY-001",
"PTO-AVS-SCALAR-MINU-DECODE-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd8681272f699413543c1770b6011a9dfc5a3c3ab68cad40c232b0a19952e10316ae00c20dc404691106f92875def496762b1214a1fa6b878c28027a08721bf9606a8adasl/scalar/alu/MINU.aslasl/scalar/alu/MINU.asl