Operands and parameters
RegDst- Reg5 destination or discard
SrcL- left Reg5 source
SrcR- right Reg5 source
SrcRType- right-source transformation selector
shamt- post-transformation logical-left-shift amount
OR applies the selected right-source transformation before its encoded logical left shift, performs bitwise inclusive OR, and publishes the PTO_XLEN result.
PTO-SCALAR-ORor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 destination or discard | Encoded zero discards the result. |
SrcL | 5 | encoding-defined | left Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcR | 5 | encoding-defined | right Reg5 source | Encoded zero reads the architectural zero GPR. |
SrcRType | 2 | encoding-defined | right-source transformation selector | Encoded zero selects .sw and sign-extends SrcR[31:0]. |
shamt | 5 | encoding-defined | post-transformation logical-left-shift amount | Encoded zero performs no shift. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| shamt | 31:27 | variable |
| SrcRType | 26:25 | variable |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b011 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b0000101 |
{
"reg": [
{
"bits": 7,
"name": "7'b0000101"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b011"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 2,
"name": "SrcRType"
},
{
"bits": 5,
"name": "shamt"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}
RegDstSrcLSrcRSrcRTypeshamtThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_OR() => ScalarOperationbegin return ScalarOperation_OR;end;readonly func InstructionContractHandler_OR() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractRightModifier_OR(encoded: bits(2)) => ScalarRightModifierbegin case encoded of when '00' => return ScalarRight_SignedWord; when '01' => return ScalarRight_UnsignedWord; when '10' => return ScalarRight_NegateOrNot; when '11' => return ScalarRight_None; end;end;
pure func InstructionContractPreparedRight_OR( right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let modifier = InstructionContractRightModifier_OR(encoded_modifier); let transformed = ApplyScalarRightModifier(right, modifier, TRUE); let shifted = LSL(transformed, shift_amount); return shifted;end;
pure func InstructionContractResult_OR( left: Word, right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let prepared_right = InstructionContractPreparedRight_OR( right, encoded_modifier, shift_amount); return ScalarBinary(ScalarBinary_OR, left, prepared_right);end;
pure func InstructionContractIsLogicalFamily_OR() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_OR() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}"],"block":[],"catalog_indices":[366],"catalog_records":[{"asm":"or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0x0000707f","match":"0x00003005","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcRType","pieces":[{"instruction_lsb":25,"value_lsb":0,"width":2}],"signedness":"encoding-defined","width":2},{"name":"shamt","pieces":[{"instruction_lsb":27,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5}],"form_id":"or_32_a7fb80e78831","length_bits":32,"mnemonic":"OR","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinary","semantic_summary":"OR applies the selected right-source transformation before its encoded logical left shift, performs bitwise inclusive OR, and publishes the PTO_XLEN result.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}"],"defaults":["SrcL, SrcR, SrcRType, shamt, and RegDst are required encoded fields; no field can be omitted.","SrcRType=00 selects .sw, SrcRType=01 selects .uw, SrcRType=10 selects .not, and SrcRType=11 selects no modifier. An omitted assembly suffix encodes SrcRType=11.","Encoded shamt zero performs no shift; every value from 0 through 31 is assigned."],"encoding_class":"standalone-encoded","examples":["or a0, a1, ->a2","or t#1, u#1.not<<1, ->u","or zero, a0.sw, ->zero"],"exceptions":["OR raises no arithmetic exception; transformation, shifting, and the final operation use PTO_XLEN bits modulo 2^PTO_XLEN.","A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before the destination effect and before TPC advances."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result.","SrcL":"Encoded zero reads the architectural zero GPR.","SrcR":"Encoded zero reads the architectural zero GPR.","SrcRType":"Encoded zero selects .sw and sign-extends SrcR[31:0].","shamt":"Encoded zero performs no shift."},"legality":["SrcL and SrcR codes 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","RegDst codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs.","All four SrcRType encodings are assigned. The logical family uses .not while the arithmetic family uses .neg; OR uses .not.","Every five-bit shamt value from 0 through 31 is legal."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 destination or discard"},{"field":"SrcL","role":"left Reg5 source"},{"field":"SrcR","role":"right Reg5 source"},{"field":"SrcRType","role":"right-source transformation selector"},{"field":"shamt","role":"post-transformation logical-left-shift amount"}],"ordering":["Snapshot both sources before the destination effect so duplicate sources, destination aliases, and queue publication use pre-instruction values.","Publish the result, then advance TPC by four bytes."],"standalone_opcode":true,"state_effects":["Transform SrcR, perform the logical left shift, and compute the bitwise inclusive OR with SrcL at PTO_XLEN width modulo 2^PTO_XLEN.","Apply the selected SrcRType transformation before the logical left shift. The transformation and shift affect SrcR only; SrcL is unchanged before the final operation.","Destination codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs; source queues are non-consuming.","No memory, reservation, descriptor, numeric-flag, trap, block, privilege, or control-flow state changes except the successful TPC advance."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-OR","mnemonic":"OR","summary":"OR applies the selected right-source transformation before its encoded logical left shift, performs bitwise inclusive OR, and publishes the PTO_XLEN result.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-OR-DECISION-BINDING-001// ndf: kind=contract level=L1 layer=scalar status=accepted// OR MUST implement the mnemonic-local canonical assembly, encoded// legality, defaults, state and memory effects, ordering, and fault boundaries// declared in this owner. The operation region below is the executable binding// for every accepted decision that names this mnemonic.// NDF-END: PTO-OR-DECISION-BINDING-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_OR() => ScalarOperationbegin return ScalarOperation_OR;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_OR() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractRightModifier_OR(encoded: bits(2)) => ScalarRightModifierbegin case encoded of when '00' => return ScalarRight_SignedWord; when '01' => return ScalarRight_UnsignedWord; when '10' => return ScalarRight_NegateOrNot; when '11' => return ScalarRight_None; end;end;
pure func InstructionContractPreparedRight_OR( right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let modifier = InstructionContractRightModifier_OR(encoded_modifier); let transformed = ApplyScalarRightModifier(right, modifier, TRUE); let shifted = LSL(transformed, shift_amount); return shifted;end;
pure func InstructionContractResult_OR( left: Word, right: Word, encoded_modifier: bits(2), shift_amount: integer {0..31}) => Wordbegin let prepared_right = InstructionContractPreparedRight_OR( right, encoded_modifier, shift_amount); return ScalarBinary(ScalarBinary_OR, left, prepared_right);end;
pure func InstructionContractIsLogicalFamily_OR() => booleanbegin return TRUE;end;
pure func InstructionContractIsWordOperation_OR() => booleanbegin return FALSE;end;// DOC-END: operation
OR is a 32-bit scalar ALU instruction. It performs bitwise inclusive OR under the complete XLEN value result rules; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then performs bitwise inclusive OR under the complete XLEN value result rules, and only afterward performs the destination effects.
SrcRType first transforms the right source; shamt then logically shifts that transformed value left before the arithmetic or logical operation.RegDst field selects the Reg5 result target or discards the result.SrcL field selects the left operand through Reg5.SrcR field selects the right operand through Reg5.SrcRType field selects the transformation applied to the right source.shamt field encodes the logical-left shift applied after right-source transformation.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
Every scalar source is snapshotted before the destination effect. The completed value is then routed through RegDst using the current scalar destination map.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 4 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
Fixed-width arithmetic follows the operation’s wraparound rule without an arithmetic exception. A fixed-bit mismatch or unavailable selected T/U source raises Fault_IllegalInstruction before publication and before TPC advances.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small OR example, SrcL=0xc, SrcR=0xa, SrcRType=11, and shamt=0 produce 0xe.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
OR MUST implement the mnemonic-local canonical assembly, encoded legality, defaults, state and memory effects, ordering, and fault boundaries declared in this owner. The operation region below is the executable binding for every accepted decision that names this mnemonic.
PTO-OR-DECISION-BINDING-001asl/scalar/alu/OR.asl70bb1b78a40d95a485fa4747b42ae0a56dfe83cdcbccbed7f70b8ac0bfd4cf947977a14a2c987ace51bc666cff3e0ade9b763eceb8960045f27c521fb91ae33b11 matching entries
PTO-AVS-SCALAR-OR-ALIASES-001tests/asl/scalar/alu/OR/scalar-bound-or-aliases-001.asl82ad093bf48b49ada6fe0f7d1c9c00e17521480c0d5a9b508d7d379222b82412PTO-AVS-SCALAR-OR-DECODE-001tests/asl/scalar/alu/OR/scalar-decode-or-canonical-001.aslcc799abb5add6a5ec6ccc5e4ebe57620b59b4771b63a6cd7e7326f8e443a8e1dPTO-AVS-SCALAR-OR-MODIFIER-001tests/asl/scalar/alu/OR/scalar-exec-or-modifier-001.asl0f4e63da408c17f079f51062d0eccf1007eb23f8509288bd22e9f3ece8a9e9a6PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/OR.md",
"id": "PTO-SCALAR-OR",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "OR",
"ndf_clause": "PTO-INST-SCALAR-OR"
},
"mnemonic": "OR",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-OR-ALIASES-001",
"PTO-AVS-SCALAR-OR-MODIFIER-001"
],
"source": "asl/scalar/alu/OR.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-OR-ALIASES-001",
"PTO-AVS-SCALAR-OR-DECODE-001",
"PTO-AVS-SCALAR-OR-MODIFIER-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd8681270bb1b78a40d95a485fa4747b42ae0a56dfe83cdcbccbed7f70b8ac0bfd4cf94637f778836d9d17bde8daaa628c4bcaefc9df63f83a7979638c58cfe514ff53basl/scalar/alu/OR.aslasl/scalar/alu/OR.aslasl/scalar/alu/OR.asl