Operands and parameters
RegDst- Reg5 destination or discard
SrcL- Reg5 source
shamt- six-bit shift amount
SRAI performs an XLEN arithmetic right shift by a six-bit immediate.
PTO-SCALAR-SRAIsrai SrcL, shamt, ->{t, u, Rd}| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 destination or discard | Encoded zero discards the result. |
SrcL | 5 | encoding-defined | Reg5 source | Encoded zero reads the architectural zero GPR. |
shamt | 6 | encoding-defined | six-bit shift amount | Encoded zero performs no shift. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| Constant | 31:26 | 6'b000000 |
| shamt | 25:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b110 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b0010101 |
{
"reg": [
{
"bits": 7,
"name": "7'b0010101"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b110"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 6,
"name": "shamt"
},
{
"bits": 6,
"name": "6'b000000"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}srai SrcL, shamt, ->{t, u, Rd}
RegDstSrcLshamtThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_SRAI() => ScalarOperationbegin return ScalarOperation_SRAI;end;readonly func InstructionContractHandler_SRAI() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractShiftWidth_SRAI() => integer {1..64}begin return 6;end;
pure func InstructionContractIsWordOperation_SRAI() => booleanbegin return FALSE;end;// PTO-INSTRUCTION: {"assembly":["srai SrcL, shamt, ->{t, u, Rd}"],"block":[],"catalog_indices":[426],"catalog_records":[{"asm":"srai SrcL, shamt, ->{t, u, Rd}","constraints":[],"encoding":[{"index":0,"mask":"0xfc00707f","match":"0x00006015","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"shamt","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":6}],"signedness":"encoding-defined","width":6}],"form_id":"srai_32_e471ea84d4fd","length_bits":32,"mnemonic":"SRAI","semantic_family":"ALU","semantic_group":"ALU","semantic_handler":"ScalarBinary","semantic_summary":"SRAI arithmetically shifts the snapshotted XLEN source right by the encoded six-bit amount and publishes the XLEN result through RegDst.","status":"accepted"}],"classification":["alu"],"contract":{"block_composition":["none"],"canonical_assembly":["srai SrcL, shamt, ->{t, u, Rd}"],"defaults":["SrcL, shamt, and RegDst are required fields; no field can be omitted.","shamt is a 6-bit shift amount from 0 through 63. Encoded zero performs an identity shift."],"encoding_class":"standalone-encoded","examples":["srai a0, 1, ->a0","srai t#1, 63, ->u","srai zero, 0, ->zero"],"exceptions":["SRAI raises no arithmetic exception; shifted-out bits are discarded and copies of SrcL[PTO_XLEN-1] enter from the left.","Bits 31:26 are fixed zero. A mismatch or unavailable T/U source raises Fault_IllegalInstruction before the destination effect and TPC advance."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the result.","SrcL":"Encoded zero reads the architectural zero GPR.","shamt":"Encoded zero performs no shift."},"legality":["SrcL codes 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4 without consumption.","RegDst codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs.","Every 6-bit shift amount from 0 through 63 is legal."],"memory_effects":["none"],"operands":[{"field":"RegDst","role":"Reg5 destination or discard"},{"field":"SrcL","role":"Reg5 source"},{"field":"shamt","role":"six-bit shift amount"}],"ordering":["Snapshot SrcL before the destination effect so aliases read the pre-instruction value.","Publish the result, then advance TPC by four bytes."],"standalone_opcode":true,"state_effects":["Compute the XLEN arithmetic right shift ASR(SrcL, shamt), inserting copies of the source sign bit at the left.","Destination codes 0 and 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write GPRs; source queues are non-consuming.","No memory, reservation, descriptor, flag, block, privilege, or control-flow state changes except the successful TPC advance."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-SRAI","mnemonic":"SRAI","summary":"SRAI performs an XLEN arithmetic right shift by a six-bit immediate.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// NDF-BEGIN: PTO-SRAI-ADR-CONTRACT-001// ndf: kind=contract level=L1 layer=scalar status=accepted// Decisions: ADR-0026.// SRAI MUST snapshot its scalar sources, apply its mnemonic-owned// width, immediate, modifier, and wrapping rule, then publish through the// assigned destination or commit effect in alias-safe order.// NDF-END: PTO-SRAI-ADR-CONTRACT-001// DOC-BEGIN: decodereadonly func InstructionContractOperation_SRAI() => ScalarOperationbegin return ScalarOperation_SRAI;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_SRAI() => ScalarSemanticHandlerbegin return ScalarHandler_ScalarBinary;end;
pure func InstructionContractShiftWidth_SRAI() => integer {1..64}begin return 6;end;
pure func InstructionContractIsWordOperation_SRAI() => booleanbegin return FALSE;end;// DOC-END: operation
SRAI is a 32-bit scalar ALU instruction. It arithmetically shifts the source right under the complete XLEN value shift rules; its current instruction contract defines the result publication path and any additional state effect.
Execution snapshots the encoded inputs, then arithmetically shifts the source right under the complete XLEN value shift rules, and only afterward performs the destination effects.
RegDst field selects the Reg5 result target or discards the result.SrcL field selects a scalar input through Reg5.shamt field encodes the six-bit shift amount.These roles come from the current instruction contract. T/U sources are read and snapshotted without being removed from their queues; exact encoded-zero meanings appear in the generated defaults below.
Every scalar source is snapshotted before the destination effect. The completed value is then routed through RegDst using the current scalar destination map.
This ALU operation has no memory effect. After its successful architectural effects, TPC advances by 4 bytes.
The operation does not introduce a hidden scalar publication target or an implicit memory access. Architectural changes remain limited to the state effects enumerated by the current contract.
All 6 encoded shift bits are assigned, giving amounts 0..63; fixed-width shifting is total and raises no arithmetic exception.
The generated legality table is authoritative for assigned field values, reserved encodings, and destination discard codes. Decode and source availability are checked before architectural effects.
This example illustrates the current ASL owner and does not replace the normative operation.
For a small SRAI example, source -8 shifted arithmetically right by 2 produces -2.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
Decisions: ADR-0026. SRAI MUST snapshot its scalar sources, apply its mnemonic-owned width, immediate, modifier, and wrapping rule, then publish through the assigned destination or commit effect in alias-safe order.
PTO-SRAI-ADR-CONTRACT-001asl/scalar/alu/SRAI.asl360c0da7e8125e712c4df415609352527c1524e9b31c8d98f5aefc0c9e9efffbb9d1ea80c0d8406ce6deca143c6cf9b471adbf3694ef1b812c94046a0f4f8fea11 matching entries
PTO-AVS-SCALAR-SRAI-DECODE-001tests/asl/scalar/alu/SRAI/scalar-decode-srai-canonical-001.aslea1e5e9bf873fdb415177f6d2c7eddd24c692f57487a79036e800de04bf41ad3PTO-AVS-SCALAR-SRAI-MAXIMUM-001tests/asl/scalar/alu/SRAI/scalar-exec-srai-maximum-001.asl8a4a93583d8a5b650fc6218654c5294fc1cdb2930f38280a2b1a674c3068b036PTO-AVS-SCALAR-SRAI-ZERO-001tests/asl/scalar/alu/SRAI/scalar-bound-srai-zero-001.asl14c84699dce2bee4fecd11a11156db015810b6f6eb0aba1102c2d9db8a00b53fPTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0026…
ADR-0026docs/status/decisions/0026-scalar-alu-totality-and-alias-order.md41d126f224dddc371832120f1b02eab64e426872fdcbea452bad77c90bdec349Loading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196Loading ADR-0084…
ADR-0084docs/status/decisions/0084-scalar-system-and-queue-operations.mde068992fa81e2c4ac46e492391a2f784141d68e041bf0b9e0586c37217d1e08c{
"classification": [
"alu"
],
"documentation": "docs/scalar/alu/SRAI.md",
"id": "PTO-SCALAR-SRAI",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "SRAI",
"ndf_clause": "PTO-INST-SCALAR-SRAI"
},
"mnemonic": "SRAI",
"readiness_subjects": [
"ADR-0026",
"ADR-0059",
"ADR-0084"
],
"semantic_tests": [
"PTO-AVS-SCALAR-SRAI-MAXIMUM-001",
"PTO-AVS-SCALAR-SRAI-ZERO-001"
],
"source": "asl/scalar/alu/SRAI.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-SRAI-DECODE-001",
"PTO-AVS-SCALAR-SRAI-MAXIMUM-001",
"PTO-AVS-SCALAR-SRAI-ZERO-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd86812360c0da7e8125e712c4df415609352527c1524e9b31c8d98f5aefc0c9e9efffbab2e676063ade27114128c8bc30b66e0b8c2cd632d16c4d418eeb3f04b1f0ef8asl/scalar/alu/SRAI.aslasl/scalar/alu/SRAI.aslasl/scalar/alu/SRAI.asl