Operands and parameters
SrcL- Reg5 byte store-value source
SrcR- Reg5 store-address source
RegDst- Reg5 success-status destination
aq- acquire ordering bit
rl- release ordering bit
far- flat-address routing hint
SC.B conditionally stores one byte when the local 64-byte-line reservation matches.
PTO-SCALAR-SC-Bsc.b SrcL, [SrcR], ->Rdsc.b.aq SrcL, [SrcR], ->Rdsc.b.rl SrcL, [SrcR], ->Rdsc.b.f SrcL, [SrcR], ->Rdsc.b.aqrl SrcL, [SrcR], ->Rdsc.b.aqf SrcL, [SrcR], ->Rdsc.b.rlf SrcL, [SrcR], ->Rdsc.b.aqrlf SrcL, [SrcR], ->Rd| Field | Bits | Signedness | Architectural role | Encoded zero |
|---|---|---|---|---|
RegDst | 5 | encoding-defined | Reg5 success-status destination | Encoded zero discards the success status. |
SrcL | 5 | encoding-defined | Reg5 byte store-value source | Encoded zero supplies numeric zero as the store value. |
SrcR | 5 | encoding-defined | Reg5 store-address source | Encoded zero reads the architectural zero register as the store address. |
aq | 1 | encoding-defined | acquire ordering bit | Encoded zero disables acquire ordering. |
far | 1 | encoding-defined | flat-address routing hint | Encoded zero selects the default flat-address route. |
rl | 1 | encoding-defined | release ordering bit | Encoded zero disables release ordering. |
Loading WaveDrom diagram… The encoding table and WaveJSON remain available below.
| Decoded item | Bit range | Value |
|---|---|---|
| Constant | 31:28 | 4'b0000 |
| far | 27 | variable |
| aq | 26 | variable |
| rl | 25 | variable |
| SrcR | 24:20 | variable |
| SrcL | 19:15 | variable |
| Constant | 14:12 | 3'b001 |
| RegDst | 11:7 | variable |
| Constant | 6:0 | 7'b0001011 |
{
"reg": [
{
"bits": 7,
"name": "7'b0001011"
},
{
"bits": 5,
"name": "RegDst"
},
{
"bits": 3,
"name": "3'b001"
},
{
"bits": 5,
"name": "SrcL"
},
{
"bits": 5,
"name": "SrcR"
},
{
"bits": 1,
"name": "rl"
},
{
"bits": 1,
"name": "aq"
},
{
"bits": 1,
"name": "far"
},
{
"bits": 4,
"name": "4'b0000"
}
],
"config": {
"bits": 32,
"fontsize": 13,
"hspace": 900,
"lanes": 1,
"offset": 0
}
}sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}
SrcLSrcRRegDstaqrlfarThis Operation comes directly from the instruction owner; the page does not rewrite its behavior.
readonly func InstructionContractOperation_SC_B() => ScalarOperationbegin return ScalarOperation_SC_B;end;readonly func InstructionContractHandler_SC_B() => ScalarSemanticHandlerbegin return ScalarHandler_StoreConditional;end;
pure func InstructionContractStoreSizeBytes_SC_B() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractReservationGranuleBytes_SC_B() => integer {1..262144}begin return PTO_RESERVATION_GRANULE_BYTES;end;
pure func InstructionContractSuccessStatus_SC_B() => Wordbegin return Zeros{PTO_XLEN};end;
pure func InstructionContractMissStatus_SC_B() => Wordbegin return Zeros{PTO_XLEN} + 1;end;
pure func InstructionContractMissIsProbeFree_SC_B() => booleanbegin return TRUE;end;// PTO-INSTRUCTION: {"assembly":["sc.b SrcL, [SrcR], ->Rd","sc.b.aq SrcL, [SrcR], ->Rd","sc.b.rl SrcL, [SrcR], ->Rd","sc.b.f SrcL, [SrcR], ->Rd","sc.b.aqrl SrcL, [SrcR], ->Rd","sc.b.aqf SrcL, [SrcR], ->Rd","sc.b.rlf SrcL, [SrcR], ->Rd","sc.b.aqrlf SrcL, [SrcR], ->Rd"],"block":[],"catalog_indices":[380],"catalog_records":[{"asm":"sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}","constraints":[],"encoding":[{"index":0,"mask":"0xf000707f","match":"0x0000100b","width_bits":32}],"encoding_kind":"L32","fields":[{"name":"RegDst","pieces":[{"instruction_lsb":7,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcL","pieces":[{"instruction_lsb":15,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"SrcR","pieces":[{"instruction_lsb":20,"value_lsb":0,"width":5}],"signedness":"encoding-defined","width":5},{"name":"aq","pieces":[{"instruction_lsb":26,"value_lsb":0,"width":1}],"signedness":"encoding-defined","width":1},{"name":"far","pieces":[{"instruction_lsb":27,"value_lsb":0,"width":1}],"signedness":"encoding-defined","width":1},{"name":"rl","pieces":[{"instruction_lsb":25,"value_lsb":0,"width":1}],"signedness":"encoding-defined","width":1}],"form_id":"sc_b_32_baf609e1d5c3","length_bits":32,"mnemonic":"SC.B","semantic_family":"AMO","semantic_group":"AMO","semantic_handler":"StoreConditional","semantic_summary":"SC.B conditionally stores one byte when the local 64-byte-line reservation matches.","status":"accepted"}],"classification":["amo"],"contract":{"block_composition":["none"],"canonical_assembly":["sc.b SrcL, [SrcR], ->Rd","sc.b.aq SrcL, [SrcR], ->Rd","sc.b.rl SrcL, [SrcR], ->Rd","sc.b.f SrcL, [SrcR], ->Rd","sc.b.aqrl SrcL, [SrcR], ->Rd","sc.b.aqf SrcL, [SrcR], ->Rd","sc.b.rlf SrcL, [SrcR], ->Rd","sc.b.aqrlf SrcL, [SrcR], ->Rd"],"defaults":["SrcL, SrcR, and RegDst are required Reg5 fields. Encoded source zero reads the architectural zero register; encoded destination zero discards the status.","aq=0 and rl=0 select relaxed ordering. aq=1 selects acquire, rl=1 selects release, and aq=1 with rl=1 selects acquire-release.","far=0 selects the default flat-address route. far=1 is a profile routing hint; the reference profile preserves the same address and reservation comparison."],"encoding_class":"standalone-encoded","examples":["sc.b a0, [a1], ->a2","sc.b.aqrl t#1, [u#1], ->u","sc.b.f zero, [sp], ->t"],"exceptions":["Every byte address is naturally aligned. On a line-matched attempt, alignment, translation, and write permission are checked after reservation clear and before memory or destination effects.","A line-matched access fault reports the original address, emits no event, preserves memory and destination, and enters the ordinary trap envelope. Recovery restores the original TPC.","A reservation miss is probe-free even for a misaligned or inaccessible address and therefore does not raise a data-access fault.","An undecodable fixed-bit pattern raises Fault_IllegalInstruction before effects. All explicit field values are assigned."],"field_contracts":{},"field_zero_meanings":{"RegDst":"Encoded zero discards the success status.","SrcL":"Encoded zero supplies numeric zero as the store value.","SrcR":"Encoded zero reads the architectural zero register as the store address.","aq":"Encoded zero disables acquire ordering.","far":"Encoded zero selects the default flat-address route.","rl":"Encoded zero disables release ordering."},"legality":["All 32 SrcL and SrcR Reg5 encodings are assigned: 0..23 select absolute GPRs, 24..27 select T#1..T#4, and 28..31 select U#1..U#4.","All 32 RegDst encodings are assigned. Code 0 and codes 24..29 discard, code 30 pushes U, code 31 pushes T, and codes 1..23 write the named absolute GPR.","All aq, rl, and far combinations are assigned. Reservation match is based only on the containing 64-byte line; LR byte address and width do not narrow it.","Every byte address is naturally aligned."],"memory_effects":["A matching reservation is cleared before access preflight. After successful preflight, store SrcL bits 7:0 as one 1-byte little-endian byte, emit one ordered store event, and publish status zero.","A missing or different-line reservation is cleared and publishes status one without alignment, translation, permission, bounded-memory probe, memory event, or memory access.","The reservation is cleared by every attempt. A line-matched access fault leaves memory and destination unchanged; after recovery, reissue without a new LR is a probe-free miss."],"operands":[{"field":"SrcL","role":"Reg5 byte store-value source"},{"field":"SrcR","role":"Reg5 store-address source"},{"field":"RegDst","role":"Reg5 success-status destination"},{"field":"aq","role":"acquire ordering bit"},{"field":"rl","role":"release ordering bit"},{"field":"far","role":"flat-address routing hint"}],"ordering":["aq=0,rl=0 records relaxed ordering; aq=1,rl=0 acquire; aq=0,rl=1 release; aq=1,rl=1 acquire-release on a successful store.","A reservation miss emits no memory event. far changes only the route hint in the reference profile."],"standalone_opcode":true,"state_effects":["Snapshot SrcL and SrcR before reservation, memory, or destination effects, including repeated GPR and same-queue aliases.","Publish status zero after a nonfaulting matching store and status one after a reservation miss. A line-matched fault publishes no status.","Clear the local reservation for success, miss, and line-matched fault before any possible trap.","Successful or miss completion advances TPC by four bytes. A line-matched fault saves the original TPC; recovery restores it, and reissue without a new LR completes as a miss."]},"depends_on":["PTO-BLOCK-MODEL-SCHEMA-PROFILE-ENCODING"],"id":"PTO-SCALAR-SC-B","mnemonic":"SC.B","summary":"SC.B conditionally stores one byte when the local 64-byte-line reservation matches.","surface":"scalar"}// PTO-REVIEW: {"review_method":"formal-definition-read","outcome":"FORMAL-COMPLETE","reviewed_fields":["assembly","encoding","defaults","operation","state","memory","ordering","faults","reserved"]}// DOC-BEGIN: decodereadonly func InstructionContractOperation_SC_B() => ScalarOperationbegin return ScalarOperation_SC_B;end;// DOC-END: decode// DOC-BEGIN: operationreadonly func InstructionContractHandler_SC_B() => ScalarSemanticHandlerbegin return ScalarHandler_StoreConditional;end;
pure func InstructionContractStoreSizeBytes_SC_B() => integer {1,2,4,8}begin return 1;end;
pure func InstructionContractReservationGranuleBytes_SC_B() => integer {1..262144}begin return PTO_RESERVATION_GRANULE_BYTES;end;
pure func InstructionContractSuccessStatus_SC_B() => Wordbegin return Zeros{PTO_XLEN};end;
pure func InstructionContractMissStatus_SC_B() => Wordbegin return Zeros{PTO_XLEN} + 1;end;
pure func InstructionContractMissIsProbeFree_SC_B() => booleanbegin return TRUE;end;// DOC-END: operation
SC.B conditionally stores one byte when the local 64-byte-line reservation matches and publishes status zero for success or one for a miss.
The ASL DOC contract selects ScalarHandler_StoreConditional with an access width of 1 byte.
Every attempt clears the reservation. A reservation miss is probe-free, while a matching attempt performs write preflight before memory or destination effects.
SrcL carries the Reg5 byte store-value source; SrcR carries the Reg5 store-address source; RegDst carries the Reg5 success-status destination; aq carries the acquire ordering bit; rl carries the release ordering bit; far carries the flat-address routing hint.
aq and rl select relaxed, acquire, release, or acquire-release ordering; far is a profile routing hint and does not change the architectural result in the reference profile.
A matching nonfaulting attempt stores the low-width source and emits one ordered store event; a miss leaves memory untouched and emits no event.
Success, miss, and line-matched fault all clear the reservation; success or miss advances TPC by 4 bytes.
Every byte address is naturally aligned. Alignment, translation, and permission checks precede architectural effects.
A reservation miss is probe-free. A line-matched fault clears the reservation but publishes no status, event, memory update, or TPC advance; recovery reissue misses without a new LR.
This example only shows one accepted spelling; the generated contract below remains authoritative.
For a first reading, use sc.b SrcL, [SrcR], ->Rd and then vary only the ordering or route modifiers described above.
Bodies come from owning ASL. Dragging or buttons change only this page-session view order.
No NDF clause is attached to this unit.
12 matching entries
PTO-AVS-SCALAR-SC-B-DECODE-001tests/asl/scalar/amo/SC.B/scalar-decode-sc-b-canonical-001.asl9809291bbb63a1428e8edb412cac365fd9917cc74045046940ddc916ffe4ee83PTO-AVS-SCALAR-SC-B-MISS-001tests/asl/scalar/amo/SC.B/scalar-bound-sc-b-miss-001.asl7cf156730ef8fa12002e9260753301e8dcafd8a354658eebdafc648421ba9bf6PTO-AVS-SCALAR-SC-B-PRECISE-001tests/asl/scalar/amo/SC.B/scalar-fault-sc-b-precise-001.asl23ad27de7414171b128a625e171c350d179e1129ecee3b00845bfdc5e547754fPTO-AVS-SCALAR-SC-B-SUCCESS-001tests/asl/scalar/amo/SC.B/scalar-exec-sc-b-success-001.asl34f0d372d8522bc9af230fe4887474e94d254ccf373d5357b0e7102e8c0af501PTO-EVIDENCE-RELEASE-TRACEABILITYPTO-EVIDENCE-RELEASE-TRACEABILITYspec/evidence/release-traceability-readiness.jsonc7327021d39dc67ac5564bc55073b3870a397d79ac8d9648284d56e33bc14a3ePTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREPTO-EVIDENCE-INSTRUCTION-CONTRACT-CLOSUREspec/evidence/instruction-contract-closure.json3ef2bb62421c79dff8fa77a1c7983923b523244b8090812883ef81286ca8106aPTO-EVIDENCE-ARCHITECTURE-READINESSPTO-EVIDENCE-ARCHITECTURE-READINESSspec/evidence/architecture-readiness.json4b0b85199101251bea744e0f3591cc31906909dc80d5ab651c417a936036a004PTO-EVIDENCE-RELEASE-GATE-READINESSPTO-EVIDENCE-RELEASE-GATE-READINESSspec/evidence/release-gate-readiness.jsona0f4d2b6920c08981ea55fd8ef820708a40d4feb5402c5150e8e9ab532d84ce0PTO-EVIDENCE-RELEASE-MANIFESTPTO-EVIDENCE-RELEASE-MANIFESTspec/release-manifest.json1a64c109ed7a90351c41e2a418b3c0ebaf8ad975838986d2101385186b85c0d8Loading ADR-0020…
ADR-0020docs/status/decisions/0020-production-memory-events-and-atomic-corners.md215b18f05d0b53120949373fce6a5ce22f7ab534fb22df24743a9b2b4beb2decLoading ADR-0030…
ADR-0030docs/status/decisions/0030-scalar-amo-totality-and-reservation.md110bd32b3004a8383913ac6053cc7d0a1d0b8e03e3ef7c47d83292c94a6a17ebLoading ADR-0059…
ADR-0059docs/status/decisions/0059-mnemonic-field-encoding-closure.mdf18d13f735cfaf9f2803c754c5818f4af33d1cc42c489f0d9ce060b07bb3a196{
"classification": [
"amo"
],
"documentation": "docs/scalar/amo/SC.B.md",
"id": "PTO-SCALAR-SC-B",
"instruction_contract": {
"artifact": "spec/evidence/instruction-contract-closure.json",
"mnemonic": "SC.B",
"ndf_clause": "PTO-INST-SCALAR-SC-B"
},
"mnemonic": "SC.B",
"readiness_subjects": [
"ADR-0020",
"ADR-0030",
"ADR-0059"
],
"semantic_tests": [
"PTO-AVS-SCALAR-SC-B-MISS-001",
"PTO-AVS-SCALAR-SC-B-PRECISE-001",
"PTO-AVS-SCALAR-SC-B-SUCCESS-001"
],
"source": "asl/scalar/amo/SC.B.asl",
"surface": "scalar",
"tests": [
"PTO-AVS-SCALAR-SC-B-DECODE-001",
"PTO-AVS-SCALAR-SC-B-MISS-001",
"PTO-AVS-SCALAR-SC-B-PRECISE-001",
"PTO-AVS-SCALAR-SC-B-SUCCESS-001"
]
}0.58.5 · Release candidate7dc8b7e5b121d2b2499a2273bebff29e2cd868120413e9fceeca9883914b129d0081b19eec962fd492782d0a4e04a547add97eebc58d2f2f6ac801255a67756d79be0e20ab11ba0e1ae45c776613fb82f233491fasl/scalar/amo/SC.B.aslasl/scalar/amo/SC.B.asl