FCVTZ

assembly

[
  "fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd}"
]

block

[]

catalog_indices

[
  94
]

catalog_records

[
  {
    "asm": "fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd}",
    "constraints": [
      {
        "field": "SrcType",
        "operator": "one-of",
        "values": [
          0,
          1
        ]
      },
      {
        "field": "DstType",
        "operator": "one-of",
        "values": [
          0,
          1,
          2,
          3,
          4,
          5,
          6,
          7,
          8,
          9,
          10,
          11,
          12,
          13,
          14
        ]
      }
    ],
    "encoding": [
      {
        "index": 0,
        "mask": "0x01f0707f",
        "match": "0x0000506b",
        "width_bits": 32
      }
    ],
    "encoding_kind": "L32",
    "fields": [
      {
        "name": "DstType",
        "pieces": [
          {
            "instruction_lsb": 27,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "RegDst",
        "pieces": [
          {
            "instruction_lsb": 7,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcL",
        "pieces": [
          {
            "instruction_lsb": 15,
            "value_lsb": 0,
            "width": 5
          }
        ],
        "signedness": "encoding-defined",
        "width": 5
      },
      {
        "name": "SrcType",
        "pieces": [
          {
            "instruction_lsb": 25,
            "value_lsb": 0,
            "width": 2
          }
        ],
        "signedness": "encoding-defined",
        "width": 2
      }
    ],
    "form_id": "fcvtz_32_bee01d31217c",
    "length_bits": 32,
    "mnemonic": "FCVTZ",
    "semantic_family": "FSU",
    "semantic_group": "FSU",
    "semantic_handler": "ConvertFloatingEncoding",
    "semantic_summary": "FCVTZ converts a selected FP64 or FP32 carrier to integer carrier code 0 through 14 with fixed round-toward-zero mode.",
    "status": "accepted"
  }
]

classification

[
  "fsu"
]

contract

{
  "block_composition": [
    "none"
  ],
  "canonical_assembly": [
    "fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd}"
  ],
  "defaults": [
    "Every displayed operand field is encoded explicitly; encoded zero is a value and never denotes omission.",
    "SrcType=0 selects an FP64 carrier and SrcType=1 selects the zero-extended low-word FP32 carrier. SrcType=2 and SrcType=3 are reserved.",
    "DstType codes 0..14 are assigned carrier widths and codes 15..31 are reserved."
  ],
  "encoding_class": "standalone-encoded",
  "examples": [
    "fcvtz.fd2sd a0, ->a1",
    "fcvtz.fs2sw t#1, ->u"
  ],
  "exceptions": [
    "A fixed-bit mismatch, reserved SrcType, reserved DstType where present, or unavailable selected T/U source raises Fault_IllegalInstruction before source, profile, destination, flag, queue, or TPC effects.",
    "Numeric profile flags update sticky status and do not themselves raise a synchronous PTO trap."
  ],
  "field_contracts": {},
  "field_zero_meanings": {
    "DstType": "Encoded zero selects the 64-bit destination carrier; it is not omission.",
    "RegDst": "Encoded zero discards the result.",
    "SrcL": "Encoded zero reads the architectural zero GPR.",
    "SrcType": "Encoded zero selects the 64-bit source carrier; it is not omission."
  },
  "legality": [
    "Every Reg5 source uses codes 0..23 for absolute GPRs, 24..27 for T#1..T#4, and 28..31 for U#1..U#4 without consumption.",
    "Every Reg5 destination is assigned: codes 1..23 write GPRs, 30 pushes U, 31 pushes T, and 0 plus 24..29 discard only the result.",
    "SrcType codes 0 and 1 are assigned; codes 2 and 3 are reserved.",
    "DstType codes 0 through 14 are assigned; codes 15 through 31 are reserved."
  ],
  "memory_effects": [
    "none"
  ],
  "operands": [
    {
      "field": "DstType",
      "role": "destination carrier selector"
    },
    {
      "field": "RegDst",
      "role": "Reg5 destination or discard"
    },
    {
      "field": "SrcL",
      "role": "left or sole Reg5 source"
    },
    {
      "field": "SrcType",
      "role": "source carrier selector"
    }
  ],
  "ordering": [
    "Validate every encoded type before the first architectural source read or profile call.",
    "Snapshot every explicit source before flag or destination effects; duplicate sources, destination aliases, and same-queue read-then-push observe pre-instruction values.",
    "Accumulate produced flags, publish or discard the destination, and then advance TPC."
  ],
  "standalone_opcode": true,
  "state_effects": [
    "FCVTZ converts a selected FP64 or FP32 carrier to integer carrier code 0 through 14 with fixed round-toward-zero mode.",
    "The selected numeric profile returns an exact NV, DZ, OF, UF, NX vector which is ORed into existing sticky CORE_STATE flags.",
    "For pto-v0, preserve the normalized source bits, retain the selected integer carrier width, and return zero flags. This executable reference behavior is not target floating-point conformance.",
    "Destination codes 1..23 write GPRs, 30 pushes U, 31 pushes T, and 0 plus 24..29 discard the result.",
    "Successful execution advances TPC by four bytes."
  ]
}

depends_on

[
  "PTO-SCALAR-MODEL-FSU-PROFILE"
]

id

PTO-SCALAR-FCVTZ

mnemonic

FCVTZ

summary

FCVTZ converts a selected FP64 or FP32 carrier to integer carrier code 0 through 14 with fixed round-toward-zero mode.

surface

scalar

{
  "classification": [
    "fsu"
  ],
  "documentation": "docs/scalar/fsu/FCVTZ.md",
  "id": "PTO-SCALAR-FCVTZ",
  "instruction_contract": {
    "artifact": "spec/evidence/instruction-contract-closure.json",
    "mnemonic": "FCVTZ",
    "ndf_clause": "PTO-INST-SCALAR-FCVTZ"
  },
  "mnemonic": "FCVTZ",
  "readiness_subjects": [
    "ADR-0028",
    "ADR-0038",
    "ADR-0039",
    "ADR-0047",
    "ADR-0059",
    "ADR-0084"
  ],
  "semantic_tests": [
    "PTO-AVS-FSU-FCVTZ-BOUND-001",
    "PTO-AVS-FSU-FCVTZ-DST-001",
    "PTO-AVS-FSU-FCVTZ-EXEC-001",
    "PTO-AVS-FSU-FCVTZ-FLAGS-001",
    "PTO-AVS-FSU-FCVTZ-ROUND-001",
    "PTO-AVS-FSU-FCVTZ-RSVD-001",
    "PTO-AVS-FSU-FCVTZ-SNAP-001",
    "PTO-AVS-FSU-FCVTZ-SRC-001",
    "PTO-AVS-FSU-FCVTZ-TYPE-001"
  ],
  "source": "asl/scalar/fsu/FCVTZ.asl",
  "surface": "scalar",
  "tests": [
    "PTO-AVS-FSU-FCVTZ-BOUND-001",
    "PTO-AVS-FSU-FCVTZ-DST-001",
    "PTO-AVS-FSU-FCVTZ-EXEC-001",
    "PTO-AVS-FSU-FCVTZ-FLAGS-001",
    "PTO-AVS-FSU-FCVTZ-ROUND-001",
    "PTO-AVS-FSU-FCVTZ-RSVD-001",
    "PTO-AVS-FSU-FCVTZ-SNAP-001",
    "PTO-AVS-FSU-FCVTZ-SRC-001",
    "PTO-AVS-FSU-FCVTZ-TYPE-001",
    "PTO-AVS-SCALAR-FCVTZ-DECODE-001"
  ]
}