Scalar And Control Instruction Set: Control And Configuration

The control-shell overview for the pto.* instruction set explains how PTO programs establish ordering, configure DMA, and manipulate predicate-visible state around tile and vector payload work.

Summary

Scalar and control operations do not carry tile payload semantics themselves. They set up the execution environment in which pto.t* and pto.v* work becomes legal and well ordered.

Main Subfamilies

This overview groups all scalar/control operations by their architectural role:

  • Pipeline sync: explicit producer-consumer edges, buffer-token protocols, and memory barriers.
  • DMA copy: loop-size and stride configuration plus GM↔vector-tile-buffer and vector-tile-buffer↔vector-tile-buffer copy operations.
  • Predicate load store: moving !pto.mask<G> state through UB and handling unaligned predicate-store streams.
  • Predicate generation and algebra: mask creation, tail masks, boolean combination, and predicate rearrangement.
  • Micro-instruction reference: scalar/vector boundary and runtime query operations.

Architectural Role

The pto.* instruction set is where PTO exposes stateful setup and synchronization explicitly. These forms are still part of the virtual ISA contract, but their visible outputs are control, mask, or configuration state rather than tile or vector payload results.

The Tile ISA instruction set (Sync and Config group) handles tile-mode configuration such as pto.sethf32mode, pto.settf32mode, pto.setfmatrix, pto.set_img2col_rpt, and pto.set_img2col_padding. These are Tile ISA instructions because they program tile-mode state; they are not in this scalar/control section.

This Control and Configuration section has no standalone operation list. Scalar/control operations are covered by the Pipeline Sync, DMA Copy, Predicate Load Store, Predicate Generation, and Micro-Instruction subfamilies.