pto.tshr

pto.tshr is part of the Elementwise Tile Tile instruction set.

Summary

Elementwise shift-right of two tiles.

Mechanism

Elementwise shift-right of two tiles.

For each element (i, j) in the valid region:

\[ \mathrm{dst}_{i,j} = \mathrm{src0}_{i,j} \gg \mathrm{src1}_{i,j} \]

Syntax

Textual spelling is defined by the PTO ISA syntax-and-operands pages.

Synchronous form:

%dst = tshr %src0, %src1 : !pto.tile<...>

AS Level 1 (SSA)

%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...>

AS Level 2 (DPS)

pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>)

C++ Intrinsic

Declared in include/pto/common/pto_instr.hpp:

template <typename TileDataDst, typename TileDataSrc0, typename TileDataSrc1, typename... WaitEvents>
PTO_INST RecordEvent TSHR(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, WaitEvents &... events);

Inputs

Operand Role Description
%src0 Left tile First source tile (value); read at (i, j) for each (i, j) in dst valid region
%src1 Right tile Second source tile (shift amount); read at (i, j) for each (i, j) in dst valid region
WaitEvents... Optional synchronisation RecordEvent tokens to wait on before issuing the operation

Expected Outputs

Result Type Description
%dst !pto.tile<...> Destination tile; all (i, j) in its valid region contain src0[i,j] >> src1[i,j] after the operation

Side Effects

No architectural side effects beyond producing the destination tile. Does not implicitly fence unrelated traffic.

Constraints

Constraints

  • Valid region:
    • The op uses dst.GetValidRow() / dst.GetValidCol() as the iteration domain.

Exceptions

Exceptions

  • Illegal operand tuples, unsupported types, invalid layout combinations, or unsupported target-profile modes are rejected by the verifier or by the selected backend instruction set.
  • Programs must not rely on behavior outside the documented legal domain of this operation, even if one backend currently accepts it.

Target-Profile Restrictions

Target-Profile Restrictions

  • Implementation checks (A2A3):

    • Supported element types are uint8_t, int8_t, uint16_t, int16_t, uint32_t, and int32_t.
    • dst, src0, and src1 must use the same element type.
    • dst, src0, and src1 must be row-major.
    • Runtime: src0.GetValidRow()/GetValidCol() and src1.GetValidRow()/GetValidCol() must match dst.

  • Implementation checks (A5):

    • Supported element types are uint8_t, int8_t, uint16_t, int16_t, uint32_t, and int32_t.
    • dst, src0, and src1 must use the same element type.
    • dst, src0, and src1 must be row-major.
    • Runtime: src0.GetValidRow()/GetValidCol() and src1.GetValidRow()/GetValidCol() must match dst.

Performance

A2/A3 Throughput

TSHR compiles to CCE vector instructions via the TBinOp.hpp performance model. The throughput is identical to TADD (binary arithmetic):

Metric Value (FP) Value (INT)
Startup latency 14 14
Completion latency 19 17
Per-repeat throughput 2 2
Pipeline interval 18 18

Examples

#include <pto/pto-inst.hpp>

using namespace pto;

void example() {
  using TileT = Tile<TileType::Vec, uint32_t, 16, 16>;
  TileT x, sh, out;
  TSHR(out, x, sh);
}

Auto Mode

# Auto mode: compiler/runtime-managed placement and scheduling.
%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...>

Manual Mode

# Manual mode: bind resources explicitly before issuing the instruction.
# Optional for tile operands:
# pto.tassign %arg0, @tile(0x1000)
# pto.tassign %arg1, @tile(0x2000)
%dst = pto.tshr %src0, %src1 : (!pto.tile<...>, !pto.tile<...>) -> !pto.tile<...>

PTO Assembly Form

%dst = tshr %src0, %src1 : !pto.tile<...>
# AS Level 2 (DPS)
pto.tshr ins(%src0, %src1 : !pto.tile_buf<...>, !pto.tile_buf<...>) outs(%dst : !pto.tile_buf<...>)