pto.vnot

pto.vnot is part of the Unary Vector Instructions instruction set.

Summary

%result holds the lane-wise bitwise inversion.

Mechanism

pto.vnot computes the lane-wise bitwise inversion: dst[i] = ~src[i]. This inverts all bits in each element. Integer element types only. Inactive lanes leave the destination unchanged.

Syntax

PTO Assembly Form

vnot %result, %input, %mask

AS Level 1 (SSA)

%result = pto.vnot %input, %mask : !pto.vreg<NxT>, !pto.mask<G> -> !pto.vreg<NxT>

Documented A5 types or forms: all integer types.

Inputs

Operand Type Description
%input !pto.vreg<NxT> Source vector register; read at each active lane i
%mask !pto.mask<G> Predicate mask; lanes where mask bit is 1 (true) are active

Expected Outputs

Result Type Description
%result !pto.vreg<NxT> Lane-wise bitwise inversion: dst[i] = ~src[i] on active lanes; inactive lanes are unmodified

Side Effects

This operation has no architectural side effect beyond producing its SSA results. It does not implicitly reserve buffers, signal events, or establish memory fences unless the form says so.

Constraints

Constraints

Integer element types only.

Exceptions

Exceptions

  • The verifier rejects illegal operand shapes, unsupported element types, and attribute combinations that are not valid for the selected instruction set or target profile.
  • Any additional illegality stated in the constraints section is also part of the contract.

Target-Profile Restrictions

Target-Profile Restrictions
  • Documented A5 coverage: all integer types.
  • A5 is the most detailed concrete profile in the current manual; CPU simulation and A2/A3-class targets may support narrower subsets or emulate the behavior while preserving the visible PTO contract.
  • Code that depends on an instruction-set-specific type list, distribution mode, or fused form should treat that dependency as target-profile-specific unless the PTO manual states cross-target portability explicitly.

Performance

Timing Disclosure

The current public VPTO timing material for PTO micro instructions remains limited. For pto.vnot, those public sources describe the instruction semantics, operand legality, and pipeline placement, but they do not publish a numeric latency or steady-state throughput.

Metric Status Source Basis
A5 latency Not publicly published Current public VPTO timing material
Steady-state throughput Not publicly published Current public VPTO timing material

If software scheduling or performance modeling depends on the exact cost of pto.vnot, treat that cost as target-profile-specific and measure it on the concrete backend rather than inferring a manual constant.

Examples

for (int i = 0; i < N; i++)
    dst[i] = ~src[i];