Vector ISA Reference

The pto.v* vector micro-instruction set of PTO ISA is organized by instruction set, with standalone per-op pages under vector/ops/.

Instruction Sets

Instruction Set Description Operations
Vector Load Store UB↔vector register transfer, gather/scatter ~25
Predicate and Materialization Vector broadcast and duplication 2
Unary Vector Instructions Single-input elementwise operations 12
Binary Vector Instructions Two-input elementwise operations 14
Vector-Scalar Instructions Vector combined with scalar operand 14
Conversion Ops Type conversion between numeric types 3
Reduction Instructions Cross-lane reductions 6
Compare and Select Comparison and conditional selection 5
Data Rearrangement Lane permutation and packing 10
SFU and DSA Instructions Special function units and DSA instructions 11

Quick Reference

Common Vector Types

Type Description
!pto.vreg<NxT> Vector register with N lanes of type T
!pto.mask<G> Predicate mask (width matches vector length)
!pto.scalar<T> Scalar register

Vector Lengths

Vector length N is a power of 2. Common values depend on the target profile.

The left sidebar provides standalone per-op pages for all vector instructions. Use the instruction set overviews above to understand shared constraints and mechanisms before reading individual opcode pages.

Source And Timing Provenance

This vector reference treats the current public VPTO semantic and timing material as the input for all per-op timing disclosures.

Timing disclosure policy for the per-op pages is intentionally strict:

  • If the public sources publish a numeric latency or throughput, the page states that number.
  • If the public sources only publish a stream-level statement, such as the one-CPI note on unaligned-load priming, the page states exactly that narrower contract.
  • If the public sources do not publish a numeric timing value, the page now says so explicitly instead of guessing.

See Also