pto.vstsx2

pto.vstsx2 is part of the Vector Load Store instruction set.

Summary

Dual interleaved store (SoA → AoS conversion).

Mechanism

pto.vstsx2 is part of the PTO vector memory/data-movement instruction set. It keeps UB addressing, distribution, mask behavior, and any alignment-state threading explicit in SSA form rather than hiding those details in backend-specific lowering.

Syntax

PTO Assembly Form

vstsx2 %low, %high, %dest[%offset], "DIST", %mask

AS Level 1 (SSA)

pto.vstsx2 %low, %high, %dest[%offset], "DIST", %mask : !pto.vreg<NxT>, !pto.vreg<NxT>, !pto.ptr<T, ub>, index, !pto.mask<G>

Inputs

%low and %high are the two source vectors, %dest is the UB base pointer, %offset is the displacement, DIST selects the interleave layout, and %mask gates the participating elements.

Expected Outputs

This op has no SSA result; it writes an interleaved stream to UB.

Side Effects

This operation writes UB-visible memory and/or updates streamed alignment state. Stateful unaligned forms expose their evolving state in SSA form, but a trailing flush form may still be required to complete the stream.

Constraints

Constraints

This instruction set is only legal for interleave distributions. The two source vectors form an ordered pair, and the interleave semantics of that pair MUST be preserved.

Exceptions

Exceptions

  • It is illegal to use addresses outside the required UB-visible space or to violate the alignment/distribution contract of the selected form.
  • Masked-off lanes or inactive blocks do not make an otherwise-illegal address valid unless the operation text explicitly says so.
  • Any additional illegality stated in the constraints section is also part of the contract.

Target-Profile Restrictions

Target-Profile Restrictions
  • A5 is the most detailed concrete profile in the current manual; CPU simulation and A2/A3-class targets may support narrower subsets or emulate the behavior while preserving the visible PTO contract.
  • Code that depends on an instruction-set-specific type list, distribution mode, or fused form should treat that dependency as target-profile-specific unless the PTO manual states cross-target portability explicitly.

Performance

Timing Disclosure

PTO-Gym v0.6 SPEC publishes a uniform 12-cycle latency for the INTLV distribution family of pto.vstsx2 on the A5 profile.

Metric Value Source Basis
A5 latency (INTLV, all element widths) 12 cycles PTO-Gym v0.6 SPEC, §III Vector Load/Store
Steady-state throughput Not publicly published Current public VPTO timing material

Other target profiles (CPU simulation, A2/A3) treat the cost as target-defined; measure on the concrete backend rather than reusing the A5 number.

Examples

// INTLV_B32:
for (int i = 0; i < 64; i++) {
    UB[base + 8*i]     = low[i];
    UB[base + 8*i + 4] = high[i];
}

Detailed Notes

Distribution modes: INTLV_B8, INTLV_B16, INTLV_B32

// INTLV_B32:
for (int i = 0; i < 64; i++) {
    UB[base + 8*i]     = low[i];
    UB[base + 8*i + 4] = high[i];
}